Serial Communications Device with Dynamic Allocation of Acceptance Masks Using Serial Implementation
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Accused Products
Abstract
A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
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Citations
40 Claims
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1-26. -26. (canceled)
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27. A filter for message acceptance in a controller area network (CAN) module, comprising:
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a filter register having a filter bit select input and a single bit filter output, wherein the filter output is sequentially coupled to each bit of a filter identifier stored in the filter register by using the filter bit select input; a bit comparator having a first input, a second input and an output, the first input is coupled to the filter output of the filter register and the second input is coupled to a message serial bit stream from a CAN interface, wherein the message serial bit stream comprises a frame identifier; bit select logic coupled to the filter bit select input of the filter register, wherein the bit select logic is synchronized with the message serial bit stream from the CAN interface; the bit comparator compares each bit of the frame identifier in the message serial bit stream with a respective bit of the filter identifier stored in the filter register, the respective bit of the filter identifier being selected by the bit select logic, wherein the bit comparator output is at a first logic level when the bit of the frame identifier and the respective bit of the filter identifier are at the same logic levels, and the bit comparator output is at a second logic level when the bit of the frame identifier and the respective bit of the filter identifier are at different logic levels; and a comparison result register coupled to the bit comparator, the comparison result register being set to the first logic level at the beginning of the message serial bit stream from the CAN interface and remains at the first logic level unless the bit comparator output goes to the second logic level then the comparison result register is reset to the second logic level, wherein if the comparison result register is at the first logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is accepted, and if the comparison result register is at the second logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is rejected. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A filter for message acceptance in a controller area network (CAN) module, comprising:
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a plurality of filter registers, each of the plurality of filter registers having a filter bit select input and a single bit output, wherein each of the filter register outputs is sequentially coupled to each bit of a respective filter identifier stored in a respective one of the plurality of filter registers by using the filter bit select inputs; a plurality of bit comparators, each of the plurality of bit comparators having a first input, a second input and an output, the first inputs are coupled to respective ones of the plurality of filter register outputs and the second inputs are coupled to a message serial bit stream from a CAN interface, wherein the message serial bit stream comprises a frame identifier; bit select logic coupled to the filter bit select inputs of the plurality of filter registers, wherein the bit select logic is synchronized with the message serial bit stream from the CAN interface; each one of the plurality of bit comparators compares each bit of the frame identifier in the message serial bit stream with respective bits of the filter identifiers stored in the plurality of filter registers, the respective bits of the filter identifiers being selected by the bit select logic, wherein the output of any one the plurality of bit comparators is at a first logic level when the bit of the frame identifier and the bit of the respective filter identifier are at the same logic levels, and the output of any one of the plurality of bit comparators is at a second logic level when the bit of the frame identifier and the respective bit of the filter identifier are at different logic levels; and a comparison result register coupled to the plurality of bit comparators, the comparison result register being set to the first logic level at the beginning of the message serial bit stream from the CAN interface and remains at the first logic level unless all of the plurality of bit comparator outputs go to the second logic level then the comparison result register is reset to the second logic level, wherein if the comparison result register is at the first logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is accepted, and if the comparison result register is at the second logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is rejected. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A method for accepting a message in a controller area network (CAN) module, said method comprising the steps of:
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storing a filter identifier in a filter register; setting a comparison result register to a first logic level; comparing each bit of a frame identifier in message serial bit stream from a CAN interface with a corresponding bit of the filter identifier, one bit at a time, and if the bit of the frame identifier and a respective bit of the identifier are at different logic levels then resetting the comparison result register to a second logic level; accepting the message serial bit stream from the CAN interface if the comparison result register is at the first logic level when the message serial bit stream is finished; and rejecting the message serial bit stream from the CAN interface if the comparison result register is at the second logic level when the message serial bit stream is finished.
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Specification