Serial Communications Device with Dynamic Allocation of Acceptance Masks Using Serial Implementation

• US 20100017490A1
• Filed: 07/16/2009
• Published: 01/21/2010
• Est. Priority Date: 09/20/2001
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Bartling, James E.
• Granted Patent: US 7,979,594 B2
• Time in Patent Office: Days
• US Class Current: 709/206
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

Claims

1-26. -26. (canceled)

27. A filter for message acceptance in a controller area network (CAN) module, comprising:

a filter register having a filter bit select input and a single bit filter output, wherein the filter output is sequentially coupled to each bit of a filter identifier stored in the filter register by using the filter bit select input;

a bit comparator having a first input, a second input and an output, the first input is coupled to the filter output of the filter register and the second input is coupled to a message serial bit stream from a CAN interface, wherein the message serial bit stream comprises a frame identifier;

bit select logic coupled to the filter bit select input of the filter register, wherein the bit select logic is synchronized with the message serial bit stream from the CAN interface;

the bit comparator compares each bit of the frame identifier in the message serial bit stream with a respective bit of the filter identifier stored in the filter register, the respective bit of the filter identifier being selected by the bit select logic, wherein

the bit comparator output is at a first logic level when the bit of the frame identifier and the respective bit of the filter identifier are at the same logic levels, and

the bit comparator output is at a second logic level when the bit of the frame identifier and the respective bit of the filter identifier are at different logic levels; and

a comparison result register coupled to the bit comparator, the comparison result register being set to the first logic level at the beginning of the message serial bit stream from the CAN interface and remains at the first logic level unless the bit comparator output goes to the second logic level then the comparison result register is reset to the second logic level, wherein

if the comparison result register is at the first logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is accepted, and

if the comparison result register is at the second logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is rejected.

28. The message acceptance filter according to claim 27, further comprising:

a mask register having a mask bit select input and a single bit mask output, the mask bit select input is coupled to the bit select logic, wherein the mask output is sequentially coupled to each bit of a mask identifier stored in the mask register by using the mask bit select input; and

reset inhibit logic coupled between the bit comparator output and the comparison result register, wherein if a respective bit of the mask identifier is at the first logic level then the comparison result register does not reset to the second logic level even if the bit comparator output is at the second logic level.

29. The message acceptance filter according to claim 27, wherein the message serial bit stream is stored in a message assembly buffer register.

30. The message acceptance filter according to claim 29, wherein the message assembly buffer register is read by a microcontroller when the message serial bit stream from the CAN interface is accepted.

31. The message acceptance filter according to claim 27, wherein the bit comparator is an EXCLUSIVE-NOR (XNOR) gate.

32. The message acceptance filter according to claim 28, wherein the reset inhibit logic is a NOR gate.

33. The message acceptance filter according to claim 27, wherein the comparison result register is a flip-flop.

34. A filter for message acceptance in a controller area network (CAN) module, comprising:

a plurality of filter registers, each of the plurality of filter registers having a filter bit select input and a single bit output, wherein each of the filter register outputs is sequentially coupled to each bit of a respective filter identifier stored in a respective one of the plurality of filter registers by using the filter bit select inputs;

a plurality of bit comparators, each of the plurality of bit comparators having a first input, a second input and an output, the first inputs are coupled to respective ones of the plurality of filter register outputs and the second inputs are coupled to a message serial bit stream from a CAN interface, wherein the message serial bit stream comprises a frame identifier;

bit select logic coupled to the filter bit select inputs of the plurality of filter registers, wherein the bit select logic is synchronized with the message serial bit stream from the CAN interface;

each one of the plurality of bit comparators compares each bit of the frame identifier in the message serial bit stream with respective bits of the filter identifiers stored in the plurality of filter registers, the respective bits of the filter identifiers being selected by the bit select logic, wherein

the output of any one the plurality of bit comparators is at a first logic level when the bit of the frame identifier and the bit of the respective filter identifier are at the same logic levels, and

the output of any one of the plurality of bit comparators is at a second logic level when the bit of the frame identifier and the respective bit of the filter identifier are at different logic levels; and

a comparison result register coupled to the plurality of bit comparators, the comparison result register being set to the first logic level at the beginning of the message serial bit stream from the CAN interface and remains at the first logic level unless all of the plurality of bit comparator outputs go to the second logic level then the comparison result register is reset to the second logic level, wherein

if the comparison result register is at the first logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is accepted, and

if the comparison result register is at the second logic level when the message serial bit stream is finished then the message serial bit stream from the CAN interface is rejected.

35. The message acceptance filter according to claim 34, further comprising:

a plurality of mask registers, each having a mask bit select input and a single bit output, the mask bit select input is coupled to the bit select logic, wherein each of the mask register outputs is sequentially coupled to each bit of a respective mask identifier stored in a respective one of the plurality of mask registers by using the mask bit select inputs; and

a multiplexer having a plurality of inputs, input selection control, and an output, each of the plurality of inputs is coupled to a respective output of the plurality of mask registers, and the input selection control determines which output of the plurality of mask registers is coupled to the output of the multiplexer;

reset inhibit logic coupled between the multiplexer output and the comparison result register, wherein if a respective bit of the mask identifier stored in the selected one of the plurality of mask registers is at the first logic level then the comparison result register does not reset to the second logic level if any one of the plurality of bit comparator outputs is at the second logic level.

36. The message acceptance filter according to claim 34, wherein the message serial bit stream is stored in a message assembly buffer register.

37. The message acceptance filter according to claim 34, wherein the message assembly buffer register is read by a microcontroller when the message serial bit stream from the CAN interface is accepted.

38. The message acceptance filter according to claim 35, wherein the multiplexer has an input coupled to the second logic level so that the reset inhibit logic does not prevent the comparison result register from being reset.

39. The message acceptance filter according to claim 35, wherein the multiplexer input selection control is coupled to a one of the plurality of filter registers, wherein additional bits in the one of the plurality of filter registers control the multiplexer.

40. A method for accepting a message in a controller area network (CAN) module, said method comprising the steps of:

storing a filter identifier in a filter register;

setting a comparison result register to a first logic level;

comparing each bit of a frame identifier in message serial bit stream from a CAN interface with a corresponding bit of the filter identifier, one bit at a time, and if the bit of the frame identifier and a respective bit of the identifier are at different logic levels then resetting the comparison result register to a second logic level;

accepting the message serial bit stream from the CAN interface if the comparison result register is at the first logic level when the message serial bit stream is finished; and

rejecting the message serial bit stream from the CAN interface if the comparison result register is at the second logic level when the message serial bit stream is finished.