TRANSACTIONAL MEMORY SUPPORT FOR NON-COHERENT SHARED MEMORY SYSTEMS USING SELECTIVE WRITE THROUGH CACHES

• US 20100017572A1
• Filed: 07/18/2008
• Published: 01/21/2010
• Est. Priority Date: 07/18/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: O'Krafka, Brian W., Koka, Pranay
• Granted Patent: US 8,108,631 B2
• Time in Patent Office: Days
• US Class Current: 711/159
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network. The method includes initiating a memory operation at a first node including a first memory controller and a transaction table where the transaction table is configured to store a list of nodes affected by the memory operation, transmitting a store request signal through the interconnect network to a second node including a second memory controller and an access table where the store request signal includes memory operation data from the first memory controller, storing memory operation data to the access table in entries corresponding to one or more memory addresses affected by the memory operation, identifying a memory conflict with one or more nodes in the list of nodes when the one or more memory addresses affected by the memory operation are also affected by one or more conflicting transactions listed in the access table, transmitting an abort signal from the second node to each of the one or more nodes corresponding to the memory conflict, and transmitting an intent to commit signal from the first node to the second node.

Claims

1. A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network, comprising:

initiating a memory operation at a first node comprising a first memory controller and a transaction table, wherein the transaction table is configured to store a list of nodes affected by the memory operation;

transmitting a store request signal through the interconnect network to a second node comprising a second memory controller and an access table, wherein the store request signal comprises memory operation data from the first memory controller;

storing memory operation data to the access table in entries corresponding to one or more memory addresses affected by the memory operation;

identifying a memory conflict with one or more nodes in the list of nodes when the one or more memory addresses affected by the memory operation are also affected by one or more conflicting transaction listed in the access table;

transmitting an abort signal from the second node to each of the one or more nodes corresponding to the memory conflict; and

transmitting an intent to commit signal from the first node to the second node.

2. The method of claim 1, further comprising:

transmitting a plurality of intent to commit signals from the first node to the nodes stored in the list of nodes in the transaction table.

3. The method of claim 1, further comprising:

transmitting a plurality of commit okay signals from the nodes stored in the list of nodes in the transaction table to the first node.

4. The method of claim 1, further comprising:

transmitting a plurality of commit done signals from the first node to the nodes stored in the list of nodes in the transaction table.

5. The method of claim 1, further comprising:

storing node identification data corresponding to a node affected by the memory operation to the transaction table.

6. The method of claim 1, further comprising:

identifying, by a compiler, the memory operation affecting the list of nodes; and

forcing a write-through of the memory operation affecting the list of nodes.

7. A method of detecting memory conflicts in a transactional shared memory system having a plurality of nodes connected through an interconnect network, comprising:

initiating a memory operation at a first node comprising a first memory controller and a transaction table, wherein the transaction table is configured to store a list of nodes affected by the memory operation;

transmitting a store request signal through the interconnect network to a second node comprising a second memory controller and an access table, wherein the store request signal comprises memory operation data from the first memory controller;

storing the memory operation data to the access table and indexing the memory operation data by memory addresses affected by the memory operation; and

identifying a memory conflict with one or more nodes when the memory addresses affected by the memory operation are also affected by one or more conflicting transactions in the access table.

8. The method of claim 7, further comprising:

transmitting a plurality of abort signals from the second node to each of the one or more nodes when the memory conflict is identified.

9. The method of claim 7, further comprising:

transmitting a plurality of intent to commit signals from the first node to the nodes stored in the list of nodes in the transaction table.

10. The method of claim 7, further comprising:

transmitting a plurality of commit okay signals from the nodes stored in the list of nodes in the transaction table to the first node.

11. The method of claim 7 further comprising:

transmitting a plurality of commit done signals from the first node to the nodes stored in the list of nodes in the transaction table.

12. The method of claim 7, further comprising:

storing node identification data corresponding to a node affected by the memory operation to the transaction table.

13. The method of claim 7, further comprising:

identifying, by a compiler, the memory operation affecting the list of nodes; and

forcing a write-through of the memory operation affecting the list of nodes.

14. A transactional shared memory system, comprising:

a plurality of nodes, each connected through an interconnect network and comprising a memory module;

a plurality of memory controllers, each corresponding to one of the plurality of nodes; and

a plurality of access tables, each corresponding to one of the plurality of memory controllers and configured to store remote operation data and memory addresses affected by a remote memory operation corresponding to the remote operation data,

wherein each of the plurality of memory controllers is configured to detect memory conflicts with one or more of the plurality of nodes.

15. The transactional shared memory system according to claim 14, wherein each of the plurality of memory controllers is further configured to store remote operation data to the corresponding one of the plurality of access tables and index the remote transaction data by memory addresses affected by the remote memory operation.

16. The transactional shared memory system according to claim 14, wherein each of the plurality of memory controllers is further configured to identify a memory conflict with one or more nodes when the memory addresses affected by the remote memory operation are also listed as affected by one or more conflicting transactions in the corresponding one of the plurality of access tables.

17. The transactional shared memory system according to claim 14, further comprising a plurality of transaction tables, each corresponding to one of the plurality of memory controllers and configured to store local transaction identification data and a list of nodes affected by a local memory operation corresponding to the local transaction identification data.

18. The transactional shared memory system according to claim 17, wherein each of the plurality of memory controllers is further configured to initiate a memory operation and store local transaction identification data and a list of nodes affected by the memory operation corresponding to the local transaction identification data to the corresponding one of the plurality of transaction tables.

19. The transactional shared memory system of claim 17, further comprising:

a compiler configured to;

identify the local memory operation affecting the list of nodes, and

force a write-through of the local memory operation affecting the list of nodes.

20. The transactional shared memory system according to claim 14, a plurality of reverse access tables, each corresponding to one of the plurality of memory controllers and configured to store transaction identification data and a list of pointers to entries in the access table corresponding to the transaction identification data.