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TRANSACTIONAL MEMORY SUPPORT FOR NON-COHERENT SHARED MEMORY SYSTEMS USING SELECTIVE WRITE THROUGH CACHES

  • US 20100017572A1
  • Filed: 07/18/2008
  • Published: 01/21/2010
  • Est. Priority Date: 07/18/2008
  • Status: Active Grant
First Claim
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1. A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network, comprising:

  • initiating a memory operation at a first node comprising a first memory controller and a transaction table, wherein the transaction table is configured to store a list of nodes affected by the memory operation;

    transmitting a store request signal through the interconnect network to a second node comprising a second memory controller and an access table, wherein the store request signal comprises memory operation data from the first memory controller;

    storing memory operation data to the access table in entries corresponding to one or more memory addresses affected by the memory operation;

    identifying a memory conflict with one or more nodes in the list of nodes when the one or more memory addresses affected by the memory operation are also affected by one or more conflicting transaction listed in the access table;

    transmitting an abort signal from the second node to each of the one or more nodes corresponding to the memory conflict; and

    transmitting an intent to commit signal from the first node to the second node.

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