NON-VOLATILE MEMORY DATA STORAGE SYSTEM WITH RELIABILITY MANAGEMENT

• US 20100017650A1
• Filed: 05/25/2009
• Published: 01/21/2010
• Est. Priority Date: 07/19/2008
• Status: Abandoned Application

• Current Assignee: Nanostar Corporation
• Original Assignee: Nanostar Corporation
• Inventors: CHIN, ROGER, Wu, Gary
• Application Number:
  US12/471,430
• Publication Number:
  US 20100017650A1
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A non-volatile memory data storage system, comprising: a host interface for communicating with an external host; a main storage including a first plurality of flash memory devices, wherein each memory device includes a second plurality of memory blocks, and a third plurality of first stage controllers coupled to the first plurality of flash memory devices; and a second stage controller coupled to the host interface and the third plurality of first stage controller through an internal interface, the second stage controller being configured to perform RAID operation for data recovery according to at least one parity.

Claims

1. A non-volatile memory data storage system with two-stage controller, comprising:

a host interface for communicating with an external host;

a main storage including

a first plurality of flash memory devices, wherein each memory device includes a second plurality of memory blocks; and

a third plurality of first stage controllers coupled to the first plurality of flash memory devices; and

a second stage controller coupled to the host interface and the third plurality of first stage controller through an internal interface, the second stage controller being configured to perform RAID operation for data recovery according to at least one parity.

2. The data storage system of claim 1, wherein the first plurality of flash devices are allocated into a number of distributed channels, wherein each channel includes the flash devices allocated into the channel and one of the first stage controllers, and further includes a DMA (Direct Memory Access) and a buffer, coupled with the one first stage controller in the same channel.

3. The data storage system of claim 2, wherein the buffer in each channel is a double-buffer including two memory buffers which are capable of operating simultaneously.

4. The data storage system of claim 1, wherein the controller maintains a remapping table for remapping a memory block to another memory block.

5. The data storage system of claim 4, wherein the remapping table includes translation between logical block addresses and physical block addresses.

6. The data storage system of claim 4, wherein each channel reserves at least one memory block as a spare block, and wherein the remapping table remaps a memory block to the spare memory block of the same channel.

7. The data storage system of claim 4, further comprising a spare memory module, and wherein the remapping table remaps a memory block to a memory block in the spare memory module.

8. The data storage system of claim 1, wherein the host interface being one of SATA, SD, SDXC, USB, SAS, Fiber Channel, PCI, eMMC, MMC, IDE and CF interface.

9. The data storage system of claim 1, wherein the flash memory devices include at least one selected from down-grade flash device and MLC_xN flash device, wherein N=2, 3, 4 or 5.

10. The data storage system of claim 1, wherein the memory devices are allocated into a plurality of regions, each region including a plurality of memory blocks of each one of the channels, and at least one of the plurality of regions including SLC flash memory devices and this one region being used as a cache memory.

11. The data storage system of claim 1, wherein the controller is configured to perform RAID-4, RAID-5 or RAID-6 operation.

12. The data storage system of claim 1, wherein the controller further comprises an XOR engine to generate the parity.

13. The data storage system of claim 1, further comprising an additional memory module coupled to the controller for more frequent access than the main storage, wherein the additional memory module is a DRAM, SRAM, SLC flash or NOR flash.

14. The data storage system of claim 13, wherein the additional memory module is detachable.

15. The data storage system of claim 13, wherein the additional memory module serves as a cache, and wherein the controller performs the following operations:

in a read operation, if a data to be read is in the cache, read it from the cache, and if a data to be read is not in the cache, read it from the main storage and write it to the cache;

in a write operation, if a data to be written has a prior version in the cache, write it to the cache, and if a data to be written does not have a prior version in the cache, read the prior version from the main storage and write the prior version to the cache before writing the data.

16. The data storage system of claim 1, wherein the controller further performs a second stage wear leveling operation across different channels.

17. The data storage system of claim 16, wherein the memory devices are allocated into a plurality of regions, and the controller performing a second stage wear leveling operation depending on an erase count or program count associated with each region.

18. The data storage system of claim 1, wherein the second-stage controller performs reliability management operation including at least one of error correction coding, error detection coding, bad block management, wear leveling, and garbage collection.

19. The data storage system of claim 1, further comprising:

a two-stage BISD circuit which detects and diagnoses the memory devices on-the-fly; and

a two-stage BISR circuit which repairs a memory device which is defected on-the-fly by bad block management.

20. The data storage system of claim 1, wherein the internal interface includes one selected from a standard NAND, LBA_NAND, BA_NAND, Flash_DIMM, ONFI NAND, Toggle-mode NAND, SATA, SD, SDXC, USB, UFS, PCI and MMC interface.

21. A non-volatile memory data storage system, comprising:

a main storage including a plurality of memory modules, wherein the data storage system performs a reliability management operation on each of the plurality of memory modules individually, the reliability management operation including at least one of error correction coding, error detection coding, bad block management, wear leveling, and garbage collection; and

a controller coupled to the main storage and configured to perform at least two kinds of RAID operations for storing data according to a first and a second RAID structure, wherein data is first stored in the main storage according to the first RAID structure and is reconfigurable to the second RAID structure;

wherein the controller reconfigures the data to the second RAID structure, or sends out a notice to reconfigure the data to the second RAID structure, according to a pre-defined reliability threshold which relates to time, erase count, program count or read count.

22. A non-volatile memory data storage system comprising:

a host interface for communicating with an external host;

a main storage including a plurality of flash devices divided into a plurality of channels;

a controller coupled to the host interface and configured to reduce erase/program cycles of the main storage;

a memory module coupled to the controller and serving as cache memory or serving as a swap space;

wherein reliability management operations including error correction coding, error detection coding, bad block management and wear leveling are performed on each channel individually.

23. A non-volatile memory data storage system, comprising:

a host interface for communicating with an external host;

a plurality of distributed channels each including

a flash memory device;

a buffer; and

a DMA (Direct Memory Access) coupled to the buffer; and

a controller coupled to the host interface and the plurality of distributed channels.