ALL AROUND GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20100019276A1
• Filed: 11/06/2008
• Published: 01/28/2010
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: JANG, Tae Su
• Granted Patent: US 8,816,427 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body

Abstract

An all around gate type semiconductor device improves mobility of electrons and holes by using a silicon germanium pillar and a silicon layer surrounding the silicon germanium pillar as a vertical channel. A gate electrode is formed to surround the vertical channel. When a semiconductor device is used as a nMOSFET, the silicon layer strained by silicon germanium is used as the channel to increase electron mobility. When the semiconductor device is used as a pMOSFET, the silicon germanium pillar is used as the channel to increase hole mobility. Thus, the semiconductor device can enhance current supply capacity regardless of transistor type.

Claims

1. An all around gate type semiconductor device comprising:

a vertical channel pillar formed over a silicon substrate and comprising germanium;

a silicon layer surrounding the vertical channel pillar; and

a gate electrode surrounding the silicon layer.

2. The all around gate type semiconductor device according to claim 1, further comprising:

a first source/drain contact connected to a top surface of the vertical channel pillar;

a second source/drain contact connected to the silicon layer; and

a gate contact connected to the gate electrode.

3. The all around gate type semiconductor device according to claim 1, wherein the vertical channel pillar is a silicon germanium (SiGe) pillar.

4. The all around gate type semiconductor device according to claim 3, wherein the SiGe pillar includes germanium ranging from 1% to 99%.

5. The all around gate type semiconductor device according to claim 3, wherein the vertical channel pillar is doped with p-type or n-type impurities.

6. The all around gate type semiconductor device according to claim 3, wherein the vertical channel pillar has a height ranging from 1 nm to 500 nm.

7. The all around gate type semiconductor device according to claim 3, wherein the vertical channel pillar has a width ranging from 1 nm to 300 nm.

8. The all around gate type semiconductor device according to claim 1, wherein the vertical channel pillar only includes germanium.

9. The all around gate type semiconductor device according to claim 1, wherein the silicon layer has a thickness ranging from 1 nm to 500 nm.

10. The all around gate type semiconductor device according to claim 1, wherein the silicon layer is doped with p-type or n-type impurities.

11. The all around gate type semiconductor device according to claim 1, further comprising a gate oxide film formed between the silicon layer and the gate electrode.

12. A method of manufacturing an all around gate type semiconductor device, the method comprising:

forming a vertical channel pillar including germanium over a silicon substrate;

forming a silicon layer surrounding the vertical channel pillar;

forming a gate electrode surrounding the silicon layer; and

forming a drain contact, a source contact and a gate contact connected to the vertical channel pillar, the silicon layer and the gate electrode, respectively.

13. The method according to claim 12, wherein the forming-a-vertical-channel-pillar includes:

forming a photoresist pattern that defines the vertical channel pillar region over the silicon substrate;

forming a SiGe layer in the pillar region by an epitaxy process using the silicon substrate as a seed;

etching and planarizing the SiGe layer; and

removing the photoresist pattern.

14. The method according to claim 13, wherein the epitaxy process is a vapor phase epitaxy process using chemical vapor of a silicon precursor and a germanium precursor.

15. The method according to claim 13, wherein the forming-a-SiGe-layer further includes doping a dopant by an in-situ method.

16. The method according to claim 13, wherein an amount of germanium relative to silicon in the SiGe layer ranges from 1 to 99%.

17. The method according to claim 12, wherein the forming-a-vertical-channel-pillar includes:

forming a photoresist pattern that defines the vertical channel pillar region over the silicon substrate;

forming a germanium layer in the pillar region by an epitaxy process;

etching and planarizing the germanium layer; and

removing the photoresist pattern.

18. The method according to claim 12, wherein the silicon layer is formed by an epitaxy process.

19. The method according to claim 19, wherein the silicon layer has a thickness ranging from 1 nm to 500 nm.

20. The method according to claim 19, wherein the forming-a-silicon-layer further includes doping a dopant over the silicon layer by an in-situ method.