Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems

• US 20100019279A1
• Filed: 03/31/2009
• Published: 01/28/2010
• Est. Priority Date: 04/02/2008
• Status: Active Grant

• Current Assignee: Hong Kong University of Science and Technology
• Original Assignee: Hong Kong University of Science and Technology
• Inventors: CHEN, Wanjun, ZHOU, Chunhua, CHEN, Jing
• Granted Patent: US 8,076,699 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.

Claims

1. An integrated power device structure, comprising:

a merged combination diode which includes a Schottky diode in parallel with a field-controlled diode; and

a heterojunction field effect transistor;

wherein both said combination diode and said transistor are integrated on a shared layer of a III-N-type semiconductor;

and wherein both said combination diode and said transistor include patterned areas where permanent negative charge has been introduced into a wider-bandgap portion of said shared layer which overlies a narrower-bandgap portion of said shared layer.

2. The structure of claim 1, wherein said permanent negative charge comprises fluorine ions.

3. The structure of claim 1, wherein said wider-bandgap portion is undoped.

4. The structure of claim 1, wherein said wider-bandgap portion comprises AlGaN.

5. The structure of claim 1, wherein said wider-bandgap portion comprises AlGaN capped by GaN.

6. The structure of claim 1, wherein said narrower-bandgap portion comprises GaN.

7-8. -8. (canceled)

9. An integrated power device, comprising:

a III-N-type semiconductor heterostructure, comprising a barrier layer overlying an active layer thereof, said barrier layer and said active layer having different bandgaps;

a first structure region comprising

an anode electrode having both an ohmic contact and also a first Schottky barrier contact to said semiconductor structure, and

a cathode electrode having an ohmic contact to said semiconductor structure;

a second structure region comprising

source and drain electrodes making ohmic contact to respective portions of said semiconductor structure, and

a gate electrode having a Schottky barrier contact to said semiconductor structure, intermediate between said source and drain electrodes; and

respective regions of permanently-trapped charge, located underneath ones of said Schottky barrier contacts in both said first and second structure regions.

10. The device of claim 9, wherein said permanently-trapped charge comprises fluorine ions.

11. The device of claim 9, wherein said barrier layer is undoped.

12. The device of claim 9, wherein said barrier layer comprises AlGaN.

13. The device of claim 9, wherein said barrier layer comprises AlGaN capped by GaN.

14. The device of claim 9, wherein said active layer comprises GaN.

17. The device of claim 9, wherein said active layer overlies a III-N buffer layer, which overlies a III-N nucleation layer.

15-16. -16. (canceled)

18-24. -24. (canceled)

25. A method for manufacturing an integrated semiconductor device, comprising the actions of:

forming a III-N-type heterostructure, comprising a barrier layer and an active layer, said barrier layer and said active layer having different bandgaps;

forming one or more isolation structures to at least partly separate said heterostructure into first and second structure regions;

fabricating a first structure, in said first structure region, which contains;

an anode electrode having both an ohmic contact and also a first Schottky barrier contact to said semiconductor structure,

a cathode electrode having an ohmic contact to said semiconductor structure, and

a first permanently negative charge-trapped region located directly underneath said first Schottky contact; and

fabricating a second structure in said second structure region, which contains;

source and drain electrodes making ohmic contact to respective portions of sand semiconductor structure, and

a gate electrode having a Schottky barrier contact to said semiconductor structure, intermediate between said source and drain electrodes; and

a second permanently negative charge-trapped region located directly underneath said second Schottky contact.

26. The method of claim 25, wherein said fabricating of the first structure and said fabricating of the second structure are completed simultaneously.

27. The method of claim 25, further comprising thermal annealing after the formation of said Schottky contacts.

28. The method of claim 25, further comprising the action of passivation with silicon nitride, silicon oxide layer, polyimide or Benzocyclobutene.

29. The method of claim 25, wherein said first and said second permanently negative charge-trapped region are produced by plasma treatment or low-energy ion implantation.

30. The method of claim 25, wherein said first and second permanently negative charge-trapped regions are produced by treatment with one of the group consisting of CF₄, SF₆, BF₃ and combinations thereof.

31. (canceled)