Method of fabricating super trench MOSFET including buried source electrode

• US 20100019316A1
• Filed: 09/29/2009
• Published: 01/28/2010
• Est. Priority Date: 04/30/2004
• Status: Abandoned Application

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Yue, Christiana, Shi, Sharon, Terrill, Kyle, Chen, Kuo-In, Lui, Kam Hong, Pattanayak, Deva N., Xu, Robert, Bai, Yuming
• Application Number:
  US12/586,906
• Publication Number:
  US 20100019316A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Claims

1. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

forming a first dielectric layer on the walls and bottom of said trench;

depositing a first layer of a conductive material in a lower portion of said trench, leaving an exposed portion of said first dielectric layer on the walls of an upper portion of said trench, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

removing said exposed portion of said first dielectric layer and a portion of said first dielectric layer that is laterally adjacent an upper portion of said first layer of conductive material, thereby exposing portions of lateral surfaces of said first conductive layer;

forming a second dielectric layer on the walls of said upper portion of said trench and on a top surface and said exposed portions of lateral surfaces of said first conductive layer;

depositing a second conductive layer in said upper portion of said trench, said first and second conductive layers vertically overlapping;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said second dielectric layer;

forming a source region of said first conductivity type abutting said second dielectric layer and forming a junction with said body region;

covering said second conductive layer with a third dielectric layer;

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region; and

forming an electrical connection between said first conductive layer and said source region.

2. The method of claim 1 wherein forming said trench comprises etching said substrate.

3. The method of claim 1 wherein said first dielectric layer comprises silicon dioxide.

4. The method of claim 1 wherein depositing said first layer of conductive material into said cavity comprises depositing doped polysilicon.

5. The method of claim 1 wherein depositing said second conductive layer into said trench comprises depositing doped polysilicon.

6. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

forming a thick dielectric layer on the walls and bottom of said trench;

depositing a first layer of a conductive material in said trench, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

removing an upper portion of said thick dielectric layer, said upper portion being located between said source electrode and said substrate, thereby forming a cavity between said substrate and said source electrode;

forming a thin dielectric layer in said cavity, a first section of said thin dielectric layer abutting a wall of said trench, a second section of said thin dielectric layer abutting a wall of said source electrode;

depositing a second conductive layer in a space between said first and second thin dielectric layers;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said first section of said thin dielectric layer;

forming a source region of said first conductivity type abutting said first section of said thin dielectric layer and forming a junction with said body region;

covering said second conductive layer with a third dielectric layer; and

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region and said source electrode.