DELAY LINE SYNCHRONIZER APPARATUS AND METHOD

• US 20100019822A1
• Filed: 09/28/2009
• Published: 01/28/2010
• Est. Priority Date: 04/05/2004
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: LaBerge, Paul A.
• Granted Patent: US 8,164,375 B2
• Time in Patent Office: Days
• US Class Current: 327/291
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Claims

1. (canceled)

2. A clock generator comprising:

a delay circuit configured to delay a first clock signal of a first clock domain by an amount to produce an output clock signal and couple the output clock signal to a downstream circuit, the delay circuit further configured to receive a control signal indicative of a change in the amount;

a synchronizer circuit configured to synchronize a second clock signal of a second clock domain with the first clock signal of the first clock domain;

a first switching element configured to decouple the delay circuit from the downstream circuit responsive in part to the control signal indicative of the change in the amount;

a second switching element configured to decouple the first clock signal from the delay circuit at a time after the delay circuit was decoupled from the downstream circuit; and

a phase storage element coupled to the delay circuit and configured to store a phase relationship between the first and second clock signals during a time when the first clock signal is decoupled from the delay circuit.

3. The clock generator of claim 2 wherein the second clock signal of the second clock domain has a higher clock frequency than the first clock signal in the first clock domain.

4. The clock generator of claim 2 wherein the second clock signal of the second clock domain has a frequency that is a multiple of the first clock signal in the first clock domain.

5. The clock generator of claim 2 wherein the first switching element comprises a multiplexer having two inputs, a first input coupled to receive an input clock signal and a second input coupled to ground.

6. The clock generator of claim 2 wherein the second switching element comprises a multiplexer having two in puts, a first input coupled to receive the output clock signal from the delay circuit and a second input coupled to ground.

7. The clock generator of claim 2 wherein the phase storage element comprises a flip-flop circuit.

8. The clock generator of claim 2 wherein the synchronizer circuit comprises a shift register configured to shift a logic level from an input terminal to an output terminal in response to the first clock signal.

9. A clock generator for generating an output clock signal at an output, comprising:

a delay circuit configured to delay an input clock signal coupled to an input by an adjustable delay to generate a delayed clock signal at an output;

a first switch circuit configured to selectively couple a clock signal to the input of the delay circuit responsive to a first control signal;

a second switch circuit configured to selectively couple the output of the delay circuit to the output of the clock generator responsive to a second control signal;

delay line synchronizer logic configured to generate the first and second control signals to control the first and second switch circuits to decouple the clock signal from the input of the delay circuit and decouple the output of the delay circuit from the output of the clock generator during adjustment of the adjustable delay; and

a phase storage logic coupled to the delay line synchronizer configured to receive the clock signal, the phase storage element further configured to store a phase relationship between the clock signal and a reference clock signal from which the clock signal is based while the second switch circuit decouples the output of the delay circuit from the output of the clock generator.

10. The clock generator of claim 9 wherein the delay line synchronizer logic is configured to generate the first and second control signals to control the first and second switch circuits to decouple the clock signal from the input of the delay circuit before the output of the delay circuit is decoupled from the output of the clock generator.

11. The clock generator of claim 9 wherein the delay line synchronizer logic is configured to generate the first and second control signals to control the first and second switch circuits to couple the output of the delay circuit to the output of the clock generator before the clock signal is coupled to the input of the delay circuit.

12. The clock generator of claim 9 wherein the delay line synchronizer logic is configured to generate the first and second control signals to control the first and second switch circuits to include a delay between when the clock signal is decoupled from the input of the delay circuit and when the output of the delay circuit is decoupled from the output of the clock generator.

13. The clock generator of claim 9 wherein the first and second switches comprise multiplexer circuits.

14. The clock generator of claim 9 wherein delay line synchronizer logic comprises:

a plurality of series coupled flip-flop circuits coupled to receive the clock signal;

a logic gate having a first input coupled to a last one of the plurality of series coupled flip-flop circuits and second input coupled to an output of another one of the plurality of series coupled flip-flop circuits; and

a flip-flop circuit coupled to receive the clock signal and coupled to an output of an intermediate one of the plurality of series coupled flip-flop circuits.

15. The clock generator of claim 9 wherein the phase storage logic comprises:

a first logic gate having a first input coupled to an output of one of the plurality of series coupled flip-flop circuits and having a second input;

a second logic gate having a first input coupled to the first input of the first logic gate and a second input; and

a flip-flop circuit having an input coupled to an output of the second logic gate and having a first output coupled to the second input of the first logic gate and having a second output coupled to the second input of the second logic gate.

16. A clock synchronizer circuit for a delay circuit having an adjustable delay, the clock synchronizer circuit comprising:

a first multiplexer having a multiplexer input to which an input clock signal is applied and a multiplexer output to which the multiplexer input is selectively coupled according to a first multiplexer control signal;

a second multiplexer having a multiplexer input to which an output of the delay is coupled and a multiplexer output to which the multiplexer input is selectively coupled according to a second multiplexer control signal;

a plurality of series coupled flip-flops configured to be clocked by the input clock signal and propagate a synchronizer control signal indicative of adjustment of the adjustable delay;

a first logic circuit configured to receive the input clock signal and coupled to an output of an intermediate one of the plurality of series coupled flip-flops, the first logic circuit configured to generate the first multiplexer control signal; and

a second logic circuit coupled to an output of one of the plurality of series coupled flip-flops before the intermediate one of the plurality of series coupled flip-flops and further coupled to an output of a last one of the plurality of series coupled flip flops, the second logic circuit configured to generate the second multiplexer control signal.

17. The clock synchronizer circuit of claim 16, further comprising clock phase relationship logic coupled to the output of the intermediate one of the plurality of series coupled flip-flops and having an output coupled to the first logic circuit, the clock phase relationship logic configured to track a phase relationship between the input clock signal and a reference clock signal from which the input clock signal is based.

18. The clock synchronizer circuit of claim 17 wherein the clock phase relationship logic comprises a flip-flop.

19. The clock synchronizer circuit of claim 16 wherein each of the plurality of series coupled flip-flops comprises a positive edge D flip-flop.

20. The clock synchronizer circuit of claim 19 wherein the first logic circuit comprises a negative edge D flip-flop.

21. The clock synchronizer circuit of claim 16 wherein the first multiplexer further includes a second input coupled to a reference voltage and is configured to couple the second input to the multiplexer output of the first multiplexer when the multiplexer input of the first multiplexer is not coupled to the multiplexer output of the first multiplexer.

22. The clock synchronizer circuit of claim 16 wherein the second multiplexer further includes a second input coupled to a reference voltage and is configured to couple the second input to the multiplexer output of the second multiplexer when the multiplexer input of the second multiplexer is not coupled to the multiplexer output of the second multiplexer.

23. The clock synchronizer circuit of claim 16, further comprising synchronizer input logic coupled to receive the synchronizer control signal and reference clock signal from which the input clock signal is based, the synchronizer input logic configured to output the synchronizer control signal to the plurality of series coupled flip flops responsive to the reference clock signal.