NOVEL SINGLE SUPPLY LEVEL SHIFTER CIRCUIT FOR MULTI-VOLTAGE DESIGNS, CAPABLE OF UP/DOWN SHIFTING

• US 20100019825A1
• Filed: 07/25/2008
• Published: 01/28/2010
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ali, Shahid, Manohar, Sujan
• Granted Patent: US 7,750,717 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

Claims

1. A system comprising:

a first circuit;

a second circuit;

a voltage source with an output voltage equal to a voltage value of the second circuit;

a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert the voltage value of a signal from the first circuit to the voltage value of the second circuit; and

a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage and a voltage source output voltage and to discharge into a specified node of the level shifter circuit when an output signal of the first circuit is at a logic state low.

2. The system of claim 1 wherein the capacitor loop circuit is comprised of a resistor circuit in series with a capacitor circuit.

3. The system of claim 2 wherein the capacitor circuit is comprised of at least one of a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) configured to function as the capacitor and an n-channel MOSFET transistor configured to function as the capacitor.

4. The system of claim 3 wherein the capacitor circuit contains a plurality of capacitors in parallel.

5. The system of claim 3:

wherein the resistor circuit is a plurality of p-channel MOSFET transistors in series configured to function as a resistor, and

wherein a resistance value of the plurality of p-channel MOSFET transistors in series is set to a specified value by scaling a width value to a length value of each of a p-channel MOSFET transistors.

6. The system of claim 3 wherein the resistor circuit is an other n-channel MOSFET transistor.

7. The system of claim 6 wherein the voltage source is coupled to the other n-channel MOSFET transistor in order to eliminate an unbuffered signal from the first circuit.

8. The system of claim 1 wherein the voltage source is the second circuit.

9. The system of claim 1 wherein the level shifter circuit is comprised of:

a complementary metal-oxide-semiconductor (CMOS) inverter coupled with an other CMOS inverter and wherein a CMOS inverter is coupled with the first circuit and the voltage source and the other CMOS inverter is coupled with the second circuit and the voltage source, and

a capacitor control circuit coupled with both the capacitor loop circuit and the voltage source to charge the capacitor circuit of the capacitor loop circuit to the voltage value of the second circuit when the output signal of the first circuit is at the logic state low.

10. The system of claim 1:

wherein the capacitor of the capacitor loop circuit discharges the first circuit output voltage into the level shifter circuit when a first circuit output voltage value is higher than a second circuit voltage value; and

wherein the capacitor of the capacitor loop circuit discharges the voltage source output voltage into a level shifter when the first circuit output voltage value is less than the second circuit voltage value.

11. A method of a level shifter comprising:

coupling a single voltage power supply to a level shifter circuit;

coupling a first circuit to the level shifter circuit;

using the first circuit to communicate a voltage signal to the level shifter circuit;

configuring the level shifter circuit to convert a voltage value of the voltage signal to an other voltage value of a second circuit;

configuring a charge holder circuit coupled to the level shifter circuit with a capacitor to charge from at least one of a first circuit output voltage and a voltage source output voltage and to discharge into a specified node of the level shifter circuit when the voltage signal is at a logic state low in order to accelerate a change of the voltage value the voltage signal to the other voltage value of the second circuit;

coupling the level shifter to the second circuit; and

using the level shifter circuit to communicate the voltage signal with the other voltage value to the second circuit.

12. The method of claim 11 wherein a single power voltage supply is the second circuit.

13. The method of claim 11 wherein the charge holder circuit is comprised of a resistor circuit in series with a capacitor circuit.

14. The method of claim 13 wherein the capacitor circuit is comprised of at least one of a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) configured to function as the capacitor and an n-channel MOSFET transistor configured to function as the capacitor.

15. The method of claim 13 wherein the resistor circuit is a plurality of p-channel MOSFET transistors in series configured to function as a resistor.

16. The method of claim 13 wherein the resistor circuit is an other n-channel MOSFET transistor.

17. The method of claim 16 wherein the second circuit is coupled to the other n-channel MOSFET transistor located in the charge holder circuit in order to eliminate an unbuffered signal from the first circuit.

18. The method of claim 11 further comprising discharging the capacitor into the specified node of the level shifter circuit during a ramp up phase of the level shifter circuit in order to decrease a duration of the ramp up phase.

19. A system of an integrated circuit comprising:

a circuit configured to convert a voltage value of an input signal to an other voltage value of an output signal;

a supply circuit associated with the circuit to provide both a single voltage power input and a ground voltage input into the circuit in order to power a conversion process of the voltage value of the input signal to the other voltage value of the output signal; and

a charge provider circuit to store a charge and to discharge the charge into the circuit in order decrease a slew rate of the output signal of the circuit.

20. The system of claim 19 wherein a charge value of the charge is at least one of the voltage value of the input signal to the other voltage value of the output signal.