AMPLIFIER EMPLOYING INTERLEAVED SIGNALS FOR PWM RIPPLE SUPRESSION

• US 20100019846A1
• Filed: 10/05/2009
• Published: 01/28/2010
• Est. Priority Date: 07/12/2006
• Status: Active Grant

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Stanley, Gerald R.
• Granted Patent: US 7,876,074 B2
• Time in Patent Office: Days
• US Class Current: 330/251
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

An amplifier having improved distortion characteristics is set forth. The amplifier includes an interleaved PWM amplifier that generates interleaved PWM pulses in response to a modified input signal and one or more carrier signals. The interleaved PWM pulses of the amplifier are used to drive a power stage, such as an opposed current power stage. The amplifier also includes an interleaved PWM generator that provides interleaved PWM pulses in response to the modified input signal and one or more further carrier signals. The carrier signals used by the PWM generator may differ in phase from the carrier signals used by the interleaved PWM amplifier to generate its interleaved PWM pulses. One or more feedback circuits are employed in the generation of the modified input signal. More particularly, the feedback circuit(s) generates the modified input signal based on an input signal that is to be amplified and the interleaved PWM pulses of the interleaved PWM generator.

Claims

1. -37. (canceled)

38. An amplifier comprising:

an interleaved PWM generator providing primary and secondary sets of interleaved PWM pulses in response to an input signal;

an interleaved PWM output stage responsive to corrected interleaved PWM pulses corresponding to the primary set of interleaved PWM pulses to generate amplified PWM output pulses;

an interleaved PWM corrector responsive to one or more correction signals derived from one or more feedforward signals corresponding to the secondary set of interleaved PWM pulses to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

39. An amplifier as claimed in claim 38, where the interleaved PWM pulses of the primary set are generated with carrier signals that differ in phase from carrier signals used to generate the interleaved PWM pulses of the secondary set.

40. An amplifier as claimed in claim 38 where the interleaved PWM corrector is further responsive to one or more feedback signals corresponding to the amplified PWM output pulses to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

41. An amplifier as claimed in claim 38 where the primary set of interleaved PWM pulses has an interleave order of N>

1, the secondary set of interleaved PWM pulses has an interleave order of L, and where N=L.

42. An amplifier as claimed in claim 38 where the primary set of interleaved PWM pulses is of an interleave order N>

1, the secondary set of interleaved PWM pulses is of an interleave order L, and where N=L.

43. An amplifier comprising:

an interleaved PWM generator providing primary and secondary sets of interleaved PWM pulses in response to an input signal;

a feedforward circuit providing one or more feedforward signals derived from the secondary set of interleaved PWM pulses;

an interleaved PWM output stage responsive to corrected interleaved PWM pulses corresponding to the primary set of interleaved PWM pulses to generate amplified PWM output pulses;

a feedback circuit providing one or more feedback signals derived from the amplified PWM output pulses;

an interleaved PWM corrector responsive to one or more correction signals derived from the one or more feedforward signals and the one or more feedback signals to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

44. An amplifier as claimed in claim 43, where the interleaved PWM pulses of the primary set are generated from carrier signals that differ in phase from carrier signals used to generate the interleaved PWM pulses of the secondary set

45. An amplifier as claimed in claim 43 where the primary set of interleaved PWM pulses is of an interleave order N, the secondary set of interleaved PWM pulses is of an interleave order L, and where N=L.

46. An amplifier as claimed in claim 43 where the feedforward circuit comprises:

a converter disposed to receive the secondary set of interleaved PWM pulses; and

a gain circuit having a transfer function H_L.

47. An amplifier as claimed in claim 45 where the feedback circuit comprises a gain circuit having a transfer function H_N.

48. An amplifier as claimed in claim 47 and further comprising a summing circuit that provides one or more summed output signals corresponding to a difference between one or more signals provided at an output of the gain circuit of the feedback circuit and one or more signals provided at an output of the gain circuit of the feedforward circuit.

49. An amplifier as claimed in claim 48 and further comprising a signal processing circuit responsive to the summed output signal to provide the one or more correction signals to the interleaved PWM corrector.