LED BACKLIGHT DRIVER SYNCHRONIZATION AND POWER REDUCTION

• US 20100020004A1
• Filed: 07/23/2008
• Published: 01/28/2010
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: SMITH, Eric
• Granted Patent: US 8,547,321 B2
• Time in Patent Office: Days
• US Class Current: 345/102
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/342 using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines

Abstract

A method and apparatus for providing a LED backlight to a LCD display screen is disclosed. In one embodiment, the apparatus includes: N LED strings, wherein N is an integer greater than or equal to two; a first circuit operable to synchronize a LED clock signal to a LCD timing signal; and a second circuit operable to generate N PWM drive signals synchronized with the LED clock signal, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees and used to drive respective ones of the N LED strings.

Claims

1. An apparatus for providing a LED backlight to a LCD display screen, comprising:

N LED strings, wherein N is an integer greater than or equal to two;

a first circuit operable to synchronize a LED clock signal to a LCD timing signal; and

a second circuit operable to generate N PWM drive signals synchronized with the LED clock signal, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees and used to drive respective ones of the N LED strings.

2. The apparatus of claim 1 wherein the first circuit comprises a phase lock loop (PLL) circuit, which includes a voltage-controlled oscillator (VCO), wherein the LCD timing signal is applied as a reference clock to a first input of the PLL and the LED clock signal is generated by the VCO.

3. The apparatus of claim 2 wherein the PLL includes a second input for receiving a frequency multiplier signal that sets the frequency of the LED clock signal to be a desired multiple (M) of a frequency of the LCD timing signal, where M is an integer greater than or equal to one.

4. The apparatus of claim 2 wherein the second circuit comprises:

a comparator having a first input for receiving a saw tooth waveform from the PLL and a second input configured to receive a LCD brightness control signal, wherein the comparator generates a duty cycle signal based on a comparison between the saw tooth waveform and the LCD brightness control signal; and

a N-channel phase shifting circuit for generating the N PWM drive signals, wherein each N PWM drive signal has a pulse width corresponding to the duty cycle signal.

5. The apparatus of claim 1 wherein the second circuit comprises:

a comparator for generating a duty cycle signal; and

a N-channel phase shifting circuit for receiving the duty cycle signal and generating the N PWM drive signals each having a pulse width corresponding to the duty cycle signal.

6. The apparatus of claim 5 further comprising a current balancing circuit coupled to the N-channel phase shifting circuit for balancing the current provided by each of the N PWM drive signals to respective ones of the N LED strings.

7. A LCD display panel having a LED backlight source, comprising:

a LCD screen;

N LED strings, where N is an integer greater than or equal to two;

a diffuser for diffusing light from the N LED strings onto a back surface of the LCD screen; and

a circuit operable to generate N pulse width modulated (PWM) drive signals used to drive respective ones of the N LED strings, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees.

8. The LCD panel of claim 7, wherein the circuit comprises:

a comparator for generating a duty cycle signal; and

a N-channel phase shifting circuit for receiving the duty cycle signal and generating the N PWM drive signals each having a pulse width corresponding to the duty cycle signal.

9. The LCD panel of claim 8, wherein the circuit further comprises a current balancing circuit coupled to the N-channel phase shifting circuit for balancing the current provided by each of the N PWM drive signals to respective ones of the N LED strings.

10. The LCD panel of claim 7, wherein the circuit comprises a synchronization circuit operable to synchronize a LED clock signal to a LCD timing signal.

11. The LCD panel of claim 10, wherein the synchronization circuit comprises a phase lock loop (PLL) circuit, which includes a voltage-controlled oscillator (VCO), wherein the LCD timing signal is applied as a reference clock to a first input of the PLL and the LED clock signal is generated by the VCO.

12. The LCD panel of claim 11 wherein the PLL includes a second input for receiving a frequency multiplier signal that sets the frequency of the LED clock signal to be a desired multiple (M) of a frequency of the LCD timing signal, where M is an integer greater than or equal to one.

13. The LCD panel of claim 11 wherein the circuit further comprises:

a comparator having a first input for receiving a saw tooth waveform from the PLL and a second input configured to receive a LCD brightness control signal, wherein the comparator generates a duty cycle signal based on a comparison between the saw tooth waveform and the LCD brightness control signal; and

a N-channel phase shifting circuit for generating the N PWM drive signals, wherein each N PWM drive signal has a pulse width corresponding to the duty cycle signal.

14. An apparatus for synchronizing a LED backlight to a LCD screen, the apparatus comprising:

a synchronization circuit operable to synchronize a LED clock signal with a LCD timing signal; and

a drive signal generation circuit, coupled to the synchronization circuit, for generating at least one drive signal used to drive the LED backlight, wherein the at least one drive signal is synchronized with the LED clock signal.

15. The apparatus of claim 14 wherein the synchronization circuit comprises:

a voltage controlled oscillator (VCO) operable to generate the LED clock signal; and

a phase lock loop (PLL), coupled to the VCO, and operable to receive the LCD timing signal and synchronize the LED clock signal with the LCD timing signal.

16. The apparatus of claim 15 wherein the drive signal generation circuit comprises:

a comparator having a first input for receiving a saw tooth waveform from the PLL and a second input configured to receive a LCD brightness control signal,

wherein the comparator generates a duty cycle signal based on a comparison between the saw tooth waveform and the LCD brightness control signal, and

wherein the at least one driving signal comprises at least one pulse width modulated (PWM) signal having a pulse width corresponding to the duty cycle signal.

17. The apparatus of claim 14 wherein the drive signal generation circuit comprises a N-channel phase shifting circuit and the at least one drive signal comprises N PWM drive signals generated by the N-channel phase shifting circuit, where N is an integer greater than or equal to two, and wherein each N PWM drive signal is phase offset with respect to another PWM drive signal by 360/N degrees and has a pulse width corresponding to the duty cycle signal.

18. An electronic device having a LCD screen for viewing images and text, comprising:

a housing;

a LCD panel at least partially contained within the housing such that the LCD screen is viewable adjacent an outside surface of the housing;

N LED strings contained within the housing, where N is an integer greater than or equal to two;

a diffuser, contained within the housing, for diffusing light from the N LED strings onto a back surface of the LCD screen; and

a circuit, contained within the housing, and operable to generate N pulse width modulated (PWM) drive signals used to drive respective ones of the N LED strings, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees.

19. The electronic device of claim 18, wherein the circuit further comprises a current balancing circuit contained within the housing and a N-channel phase shifting circuit for balancing a current provided by each of the N PWM drive signals to respective ones of the N LED strings.

20. The electronic device of claim 18, wherein the circuit further comprises a synchronization circuit operable to synchronize a LED clock signal to a LCD timing signal, wherein the N PWM drive signals are synchronized with respect to the LED clock signal.

21. The electronic device of claim 20, wherein the synchronization circuit comprises a phase lock loop (PLL) circuit, which includes a voltage-controlled oscillator (VCO), wherein the LCD timing signal is applied as a reference clock to a first input of the PLL, and the LED clock signal is generated by the VCO.

22. A method of providing a LED backlight to a LCD display screen, comprising:

synchronizing a LED clock signal to a LCD timing signal; and

generating N PWM drive signals synchronized with the LED clock signal, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees and used to drive respective ones of N LED strings, where N is an integer greater than or equal to two; and

directing light emitted by the N LED strings onto a back surface of the LCD display screen.

23. The method of claim 22 further comprising applying the LCD timing signal to a first input of a phase lock loop (PLL) circuit, which includes a voltage-controlled oscillator (VCO), wherein the LCD timing signal is applied as a reference clock to the first input of the PLL and the LED clock signal is generated by the VCO.

24. The method of claim 23 further comprising setting the frequency of the LED clock signal to be a desired multiple (M) of a frequency of the LCD timing signal, where M is an integer greater than or equal to one.

25. The method of claim 22 further comprising:

generating a duty cycle signal; and

generating the N PWM drive signals such that each N PWM drive signal has a pulse width corresponding to the duty cycle signal.

26. The method of claim 25 further comprising balancing a current provided by each of the N PWM drive signals to respective ones of the N LED strings.

27. A method of providing a backlight from N LED strings to a LCD screen, comprising:

generating N pulse width modulated (PWM) drive signals used to drive respective ones of the N LED strings, and

wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees, where N is an integer greater than or equal to two.

28. The method of claim 27, further comprising:

generating a duty cycle signal; and

generating the N PWM drive signals such that each PWM drive signal has a pulse width corresponding to the duty cycle signal.

29. The method of claim 28 wherein the pulse width of each PWM drive signal corresponds to a duty cycle of (100/N)% such that the N LED strings cumulatively provide substantially continuous backlight illumination.

30. The method of claim 28, further comprising balancing the current provided by each of the N PWM drive signals to respective ones of the N LED strings.

31. The method of claim 27, further comprising:

synchronizing a LED clock signal to a LCD timing signal; and

synchronizing at least one of the N PWM drive signals with the LED clock signal.

32. A method of synchronizing a LED backlight to a LCD screen, comprising:

receiving a LCD timing signal;

generating a LED clock signal;

synchronizing the LED clock signal with the LCD timing signal; and

generating at least one drive signal used to drive the LED backlight, wherein the at least one drive signal is synchronized with the LED clock signal.

33. The method of claim 32 further comprising generating a duty cycle signal, wherein the at least one driving signal comprises at least one pulse width modulated (PWM) signal having a pulse width corresponding to the duty cycle signal.

34. The method of claim 32 wherein generating at least one drive signal comprises generating N PWM drive signals, where N is an integer greater than or equal to two, and offsetting each PWM drive signal with respect to another PWM drive signal by 360/N degrees in phase.

35. An apparatus for providing a LED backlight to a LCD display screen, comprising:

means for synchronizing a LED clock signal to a LCD timing signal;

means for generating N PWM drive signals synchronized with the LED clock signal, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees and used to drive respective ones of N LED strings provided by the LED backlight, where N is an integer greater than or equal to two; and

means for directing light emitted by the N LED strings onto a back surface of the LCD display screen.

36. The apparatus of claim 35 further comprising means for setting the frequency of the LED clock signal to be a desired multiple (M) of a frequency of the LCD timing signal, where M is an integer greater than or equal to one.

37. The apparatus of claim 35 further comprising:

means for generating a duty cycle signal; and

means for generating the N PWM drive signals such that each N PWM drive signal has a pulse width corresponding to the duty cycle signal.

38. The apparatus of claim 37 further comprising means for balancing a current provided by each of the N PWM drive signals to respective ones of the N LED strings.

39. An apparatus for providing a backlight from N LED strings to a LCD screen, comprising:

means for generating N pulse width modulated (PWM) drive signals used to drive respective ones of the N LED strings, wherein the N PWM drive signals are phase offset from each other by a multiple of 360/N degrees, where N is an integer greater than or equal to two.

40. The apparatus of claim 39, further comprising:

means for generating a duty cycle signal; and

means for generating the N PWM drive signals such that each PWM drive signal has a pulse width corresponding to the duty cycle signal.

41. The apparatus of claim 39 further comprising:

means for synchronizing a LED clock signal to a LCD timing signal; and

means for synchronizing at least one of the N PWM drive signals with the LED clock signal.

42. An apparatus for synchronizing a LED backlight to a LCD screen, comprising:

means for receiving a LCD timing signal;

means for generating a LED clock signal;

means for synchronizing the LED clock signal with the LCD timing signal; and

means for generating at least one drive signal used to drive the LED backlight, wherein the at least one drive signal is synchronized with the LED clock signal.

43. The apparatus of claim 42 wherein the means for generating at least one drive signal comprises means for generating N PWM drive signals, where N is an integer greater than or equal to two, and means for offsetting each PWM drive signal with respect to another PWM drive signal by 360/N degrees in phase.