RF shielding arrangement for semiconductor packages

• US 20100020518A1
• Filed: 07/28/2008
• Published: 01/28/2010
• Est. Priority Date: 07/28/2008
• Status: Abandoned Application

• Current Assignee: Anadigics Incorporated (Coherent Corp.)
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Bustamante, Ulysses T.
• Application Number:
  US12/220,757
• Publication Number:
  US 20100020518A1
• Time in Patent Office: Days
• US Class Current: 361/818
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2201/09036 : Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 2201/0909 : Preformed cutting or breaking line
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A packaging for semiconductor modules such as multi chip modules (MCM). At least one via is created on saw street region of a substrate having circuit components. The substrate is transfer molded and the transfer molded substrate is partially singulated from a first surface along with the via to create a groove. The partially singulated substrate including the groove on the saw street region and the via is coated or plated with a conducting material for RF shielding. Accordingly, the conducting material and a ground terminal of the substrate are connected through the via on the substrate.

Claims

1. A method for packaging a semiconductor module, the semiconductor module comprising a substrate, and a plurality of circuit components, the plurality of circuit components being formed on the substrate, the method comprising the steps of:

creating at least one via on the saw street region of the substrate;

transfer molding a first surface of the substrate with a molding compound;

partially singulating the transfer molded substrate from the first surface of the substrate to create a kerf on the saw street region, wherein the singulation is performed through the molding compound and the at least one via;

plating the transfer molded substrate with a shielding material, wherein a ground pad of the substrate is connected to the shielding material through the at least one via; and

singulating the substrate from a second surface, the second surface being opposite to the first surface.

2. The method according to claim 1 wherein the shielding material is a conductive material, the conducting material providing a radio frequency interference shield or an electromagnetic interference shield.

3. The method according to claim 1 wherein the substrate is a single layer substrate.

4. The method according to claim 1 wherein the substrate is a multi-layer substrate.

5. The method according to claim 1 wherein the at least one via is a blind via.

6. The method according to claim 1 wherein the at least one via is a plated through hole via.

7. A packaging arrangement for a printed circuit board having a plurality of semiconductor components mounted thereon, comprising:

a substrate, the substrate mounting the plurality of semiconductor components;

a ground pad on the lower surface of the substrate;

at least one via on the substrate, the via comprising conductive means connected to the ground pad;

a non conductive molding compound surrounding the plurality of semiconductor components; and

a conductive material deposited on said molding compound to from an RF shield, the conductive material being electrically connected to the at least one via and thereby to the ground pad.

8. The arrangement according to claim 7 wherein the conductive material deposited on the molding compound comprises a metal.

9. The arrangement according to claim 7 wherein the conductive material deposited on the molding compound comprises a conductive plastic.

10. The arrangement according to claim 7 wherein the at least one via is a plated through hole via.

11. The arrangement according to claim 7 wherein the substrate is a single layer substrate.

12. The arrangement according to claim 7 wherein the substrate is a multi layer substrate.

13. The arrangement according to claim 7 wherein at least one via is a blind via.