WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME

• US 20100020606A1
• Filed: 10/02/2009
• Published: 01/28/2010
• Est. Priority Date: 01/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yamada, Shigekazu
• Granted Patent: US 7,872,920 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.

Claims

1. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows, each row of memory cells coupled to a respective word line;

a voltage selection circuit operable to selectively supply one of at least two voltages to an output node depending upon the nature of an operation being performed by the non-volatile memory device; and

a plurality of word line control circuits coupled to the output node of the voltage selection circuit, each of the word line control circuits coupled to a respective word line in the array of non-volatile memory cells and being operable to selectively couple the voltage supplied to the output node to the respective word line.

2. The non-volatile memory device of claim 1 wherein the memory device is operable to receive a row address, and wherein the word line control circuits are operable to couple the output node to the respective word lines responsive to the row address.

3. The non-volatile memory device of claim 1 wherein the voltage selection circuit comprises:

a program voltage selection circuit operable to supply a programming voltage to a programming voltage node during a programming operation;

a bias voltage selection circuit operable to supply one of at least two bias voltages to a bias voltage output node; and

an enable voltage selection circuit operable to supply one of at least two enable voltages to an enable voltage output node depending upon whether the memory device is performing a read operation or a programming operation.

4. The non-volatile memory device of claim 3 wherein the array of non-volatile memory cells comprises multi-level memory cells configured to store a predetermined number of data bits, and wherein the bias voltage selection circuit is operable to supply one of a plurality of voltages corresponding to the predetermined number of data bits to perform a reading operation on a selected row of multi-level memory cells.

5. The non-volatile memory device of claim 3 wherein each of the word line control circuits comprises:

a first switch operable to couple the programming voltage node to the respective word line during a programming operation;

a second switch operable to couple the bias voltage node to the respective word line during a read operation if the memory cells coupled to the word line are in a selected row; and

a third switch operable to couple the enable voltage output node to the respective word line during a program operation or a read operation if the memory cells coupled to the word line are in a non-selected row.

6. The non-volatile memory device of claim 5 wherein the first, second and third switches each comprises an NMOS transistor controlled by a high voltage enable circuit, the high voltage enable circuit operable to provide a predetermined voltage level to turn the NMOS transistor ON responsive to a select control signal.

7. The non-volatile memory device of claim 1 further comprising a voltage discharging circuit coupled to the output node, the voltage discharging circuit operable to gradually discharge the output node after a memory operation is completed.

8. The non-volatile memory device of claim 1 further comprising a stand-by switch coupled to the output node, the stand-by switch operable to disable the respective word line in the array of the non-volatile memory cells by coupling the output node to ground when the array of the non-volatile memory cells are inactive.

9-16. -16. (canceled)

17. A processor-based system comprising:

a processor operable to process data and to provide memory commands and addresses;

an input device coupled to the processor;

an output device coupled to the processor; and

a non-volatile memory device comprising;

an array of non-volatile memory cells arranged in rows, each row of memory cells coupled by a word line;

a voltage selection circuit operable to selectively supply one of at least two voltages to an output node depending upon the nature of the memory commands provided by the processor; and

a plurality of word line control circuits coupled to the output node of the voltage selection circuit, each of the word line control circuits coupled to a respective word line in the array of non-volatile memory cells and being operable to selectively couple the voltage supplied to the output node to the respective word line.

18. The processor-based system of claim 17 wherein the memory device is operable to receive a row address from the processor, and wherein the word line control circuits are operable to couple the voltage supplied to the output node to the respective word lines responsive to the row address provided by the processor.

19. The processor-based system of claim 17 wherein the voltage selection circuit comprises:

a program voltage selection circuit operable to supply a programming voltage to a programming voltage node responsive to a a programming command provided by the processor;

a bias voltage selection circuit operable to supply one of at least two bias voltages to a bias voltage output node responsive to a read command provided by the processor; and

an enable voltage selection circuit operable to supply one of at least two enable voltages to an enable voltage output node depending upon whether the processor is providing a read command or a programming command.

20. The processor-based system of claim 19 wherein the array of non-volatile memory cells comprises multi-level memory cells configured to store a predetermined number of data bits, and wherein the bias voltage selection circuit is operable to supply one of a plurality of voltages corresponding to the predetermined number of data bits to perform a reading operation on a selected row of multi-level memory cells.

21. The processor-based system of claim 17 wherein each of the word line control circuits comprises:

a first switch operable to couple the programming voltage node to the respective word line responsive to a programming command provided by the processor;

a second switch operable to couple the bias voltage node to the respective word line responsive to a read command provided by the processor if the memory cells coupled to the word line are in a selected row; and

a third switch operable to couple the enable voltage output node to the respective word line responsive to a program command provided by the processor or a read command provided by the processor if the memory cells coupled to the word line are in a non-selected row.

22. The processor-based system of claim 17 further comprising a voltage discharging circuit coupled to the output node, the voltage discharging circuit operable to gradually discharge the output node after an operation responsive to a memory command from the processor is completed.

23. The processor-based system of claim 17 further comprising a stand-by switch coupled to the output node, the stand-by switch operable to disable the respective word line in the array of the non-volatile memory cells by coupling the output node to ground when the array of the non-volatile memory cells are inactive.

24-43. -43. (canceled)