Soft Errors Handling in EEPROM Devices

• US 20100020616A1
• Filed: 10/01/2009
• Published: 01/28/2010
• Est. Priority Date: 05/20/1992
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Craig, Jeffrey, Norman, Robert D., Auclair, Daniel L.
• Granted Patent: US 7,839,685 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1. A solid-state memory system comprising:

an array of memory cells, each cell capable of having its threshold voltage programmed or erased to an intended level within a range supported by the memory system;

monitoring means invoked at predefined events of the memory system for identifying any cells whose threshold voltage has shifted beyond a predetermined margin from its intended level; and

writing means for re-writing the threshold voltage of each said identified cells back to its intended level.

2-34. -34. (canceled)