NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM

• US 20100020618A1
• Filed: 07/07/2009
• Published: 01/28/2010
• Est. Priority Date: 07/22/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Sang-Won, Kim, Chan-Ho
• Granted Patent: US 8,295,092 B2
• Time in Patent Office: Days
• US Class Current: 365/185.230
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Claims

1. A nonvolatile memory device comprising:

a plurality of memory cells connected to a wordline and arranged in a row direction;

bitlines connected to the plurality of memory cells, respectively; and

a bitline bias circuit configured to separately control bias voltages applied to the bitlines according to respective locations of the memory cells along the row direction.

2. The nonvolatile memory device of claim 1, wherein the bitline bias circuit controls the bias voltages to equalize respective voltage differentials between the wordline and the bit lines at the plurality of memory cells.

3. A nonvolatile memory device comprising:

a plurality of wordlines;

a plurality of bitlines intersecting the plurality of wordlines;

a wordline driver configured to select the plurality of wordlines; and

a bitline bias circuit configured to separately bias the respective bitlines according to distances between the respective bitlines and the wordline driver.

4. The nonvolatile memory device of claim 3, wherein the bitline bias circuit comprises:

a drive circuit configured to output a preset voltage; and

a division circuit configured to divide an output voltage of the drive circuit and provide the divided output voltage to the respective bitlines.

5. The nonvolatile memory device of claim 4, wherein the division circuit comprises:

a conductive line having the same configuration as each of the plurality of wordlines and intersecting the plurality of bitlines; and

a plurality of diodes electrically connected to the conductive line and the respective bitlines.

6. The nonvolatile memory device of claim 4, wherein the memory cell array further comprises a dummy wordline;

and

wherein the division circuit comprises the dummy wordline and a plurality of dummy memory cells connected to the dummy wordline.

7. The nonvolatile memory device of claim 6, wherein a source region of the respective dummy memory cells is electrically connected to a corresponding bitline.

8. The nonvolatile memory device of claim 7, wherein a drain region of the respective dummy memory cells is electrically connected to a corresponding bitline.

9. The nonvolatile memory device of claim 6, wherein a control gate and a charge storage layer of the respective dummy memory cells are electrically connected to each other.

10. The nonvolatile memory device of claim 3, wherein the bitline bias circuit applies a first voltage to a first bitline and applies a second voltage to a second bitline, the second voltage being lower than the first voltage;

and

wherein a distance between the row decoder and the first bitline is shorter than a distance between the row decoder and the second bitline.

11. The nonvolatile memory device of claim 3, wherein the bitline bias circuit biases bitlines to be programmed among the plurality of bitlines.

12. The nonvolatile memory device of claim 3, further comprising:

a page buffer connected to the plurality of bitlines,

wherein a program inhibit voltage is applied from the page buffer to program-inhibited bitlines among the plurality of bitlines.

13. The nonvolatile memory device of claim 3, wherein the bitline bias circuit equalizes a difference between a wordline voltage and a bitline voltage applied to the respective memory cells at the plurality of memory cells.

14. The nonvolatile memory device of claim 3, wherein the bitline bias circuit is activated during a program operation.

15. The nonvolatile memory device of claim 3, further comprising:

a string selection transistor connected to the respective bitlines;

ground selection transistors connected to a common source line; and

memory cells coupled between the string selection transistor and a corresponding ground selection transistor,

wherein the bitline bias circuit biases a voltage lower than a program inhibit voltage to memory cells to be programmed.

16. A memory system comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device comprises;

a memory cell array including a plurality of wordlines and a plurality of bitlines;

a row decoder configured to select the plurality of wordlines; and

a bitline bias circuit configured to separately bias the respective bitlines according to distances between the respective bitlines and the row decoder during a program operation.

17. The memory system of claim 16, wherein the controller communicates with an external host.

18. The memory system of claim 16, wherein the nonvolatile memory device and the controller are integrated into one semiconductor device.

19. The memory system of claim 16, wherein the nonvolatile memory device and the controller constitute a solid-state disk (SSD).

20. The memory system of claim 16, wherein the nonvolatile memory device and the controller constitute a memory card.