DRY ETCH STOP PROCESS FOR ELIMINATING ELECTRICAL SHORTING IN MRAM DEVICE STRUCTURES

• US 20100022030A1
• Filed: 09/02/2009
• Published: 01/28/2010
• Est. Priority Date: 03/16/2006
• Status: Active Grant

• Current Assignee: OEM Group, LLC
• Original Assignee: Tegal Corp. (Rennova Health, Inc.)
• Inventors: Ditizio, Robert Anthony
• Granted Patent: US 7,955,870 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: A61P 17/02 for treating wounds, ulcers, burns, scars, keloids, or the like
• CPC Class Codes: A61P 25/00 Drugs for disorders of the nervous system
• CPC Class Codes: A61P 25/06 Antimigraine agents
• CPC Class Codes: A61P 27/02 Ophthalmic agents
• CPC Class Codes: A61P 29/00 Non-central analgesic, antipyretic or antiinflammatory agents, e.g. antirheumatic agents; Non-steroidal antiinflammatory drugs [NSAID]
• CPC Class Codes: A61P 3/10 for hyperglycaemia, e.g. antidiabetics
• CPC Class Codes: A61P 35/00 Antineoplastic agents
• CPC Class Codes: A61P 43/00 Drugs for specific purposes, not provided for in groups A61P1/00-A61P41/00
• CPC Class Codes: A61P 9/04 Inotropic agents, i.e. stimulants of cardiac contraction; Drugs for heart failure
• CPC Class Codes: A61P 9/10 for treating ischaemic or atherosclerotic diseases, e.g. antianginal drugs, coronary vasodilators, drugs for myocardial infarction, retinopathy, cerebrovascula insufficiency, renal arteriosclerosis
• CPC Class Codes: C07D 401/04 directly linked by a ring-member-to-ring-member bond

Abstract

The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.

Claims

1. A process for fabricating a device wherein the device comprising a top conductive layer over an insulating layer over a substrate, the process comprising:

(a) removing a portion of the top conductive layer; and

(b) selectively removing the remaining top conductive layer with respect to the underlying insulating layer.

2. A process as in claim 1 wherein removing a portion of the top conductive layer uses a mixture of fluorine- and chlorine-containing gas.

3. A process as in claim 2 wherein the chlorine-containing gas comprises Cl₂, BCl₃, HCl, chlorine-containing gas, or any combination thereof.

4. A process as in claim 2 wherein the fluorine-containing gas comprises CF₄, SF₆, CHF₃, fluorine-containing gas, or any combination thereof.

5. A process as in claim 2 wherein a ratio of chlorine-containing gas to fluorine-containing gas is in a range of 2:

1 to 20;

1.

6. A process as in claim 1 wherein removing a portion of the top conductive layer uses a mixture of NH₃ and CO gas.

7. A process as in claim 1 wherein selective removing comprises applying a bias to the substrate with bias power between a sputter threshold of the top conductive layer and the insulating layer to selectively remove the top conductive layer with respect to the underlying insulating layer.

8. A process as in claim 1 wherein the device is a magnetic junction memory device.

9. A process as in claim 1 wherein the device further comprises a bottom conductive layer under the insulation layer.

10. A process as in claim 1 wherein the insulating layer comprises aluminum oxide, magnesium oxide, or any insulating oxide.

11. A process as in claim 1 wherein the top conductive layer comprises a magnetic layer, part of an MRAM stack structure, or one or more layers of NiFe, CoFe, CoNiFe, and CoFeB.

12. A process for fabricating a device comprising:

(a) providing a substrate;

(b) forming an insulating layer over the substrate;

(c) forming a top conductive layer over the insulating layer;

(d) removing a portion of the top conductive layer; and

(e) selectively removing the remaining top conductive layer with respect to the underlying insulating layer.

13. A process as in claim 12 wherein removing a portion of the top conductive layer uses a mixture of fluorine- and chlorine-containing gas.

14. A process as in claim 12 wherein the chlorine-containing gas comprises Cl₂, BCl₃, HCl, chlorine-containing gas, or any combination thereof.

15. A process as in claim 12 wherein the fluorine-containing gas comprises CF₄, SF₆, CHF₃, fluorine-containing gas, or any combination thereof.

16. A process as in claim 12 wherein a ratio of chlorine-containing gas to fluorine-containing gas is in a range of 2:

1 to 20;

1.

17. A process as in claim 12 wherein removing a portion of the top conductive layer uses a mixture of NH₃ and CO gas.

18. A process as in claim 12 wherein the device is a magnetic junction memory device.

19. A process as in claim 12 further comprising the step of forming a bottom conductive layer under the insulation layer.

20. A process as in claim 12 wherein the insulating layer comprises aluminum oxide, magnesium oxide, or any insulating oxide.

21. A process as in claim 12 wherein the top conductive layer comprises a magnetic layer, part of an MRAM stack structure, or one or more layers of NiFe, CoFe, CoNiFe, and CoFeB.

22. A process for fabricating a device comprising:

(a) providing a substrate;

(b) forming an insulating layer over the substrate;

(c) forming a top conductive layer over the insulating layer;

(d) removing a portion of the top conductive layer; and

(e) applying a bias to the substrate with bias power between the sputter threshold of the top conductive layer and the insulating layer to selectively remove the top conductive layer with respect to the underlying insulating layer.

23. A process as in claim 22 wherein removing a portion of the top conductive layer uses a mixture of fluorine- and chlorine-containing gas.

24. A process as in claim 22 wherein the chlorine-containing gas comprises Cl₂, BCl₃, HCl, chlorine-containing gas, or any combination thereof.

25. A process as in claim 22 wherein the fluorine-containing gas comprises CF₄, SF₆, CHF₃, fluorine-containing gas, or any combination thereof.

26. A process as in claim 22 wherein a ratio of chlorine-containing gas to fluorine-containing gas is in a range of 2:

1 to 20;

1.

27. A process as in claim 22 wherein removing a portion of the top conductive layer uses a mixture of NH₃ and CO gas.

28. A process as in claim 22 further comprising applying at least one of a non-reactive gas ambient, <

1% of an oxygen-containing gas, a mixture of a non-reactive gas and <

1% of an oxygen-containing gas, an etch process using a mixture of a non-reactive gas and <

1% of an oxygen-containing gas, and a physical sputter process using a mixture of a non-reactive gas and <

1% of an oxygen-containing gas.

29. A process as in claim 28 wherein the non-reactive gas is Ar, He, Ne, Kr, N₂, or Xe, or any combination thereof, and wherein the oxygen-containing gas is O, O₂, N₂O, NO, air, CO, or any combination thereof.

30. A process as in claim 28 wherein the mixture is 99.9% Ar and 0.1% O₂.

31. A process as in claim 28 wherein the mixture of a non-reactive gas and an oxygen-containing gas is introduced through a first flow controller and a non-reactive gas is introduced through a second flow controller.

32. A process as in claim 31 wherein the first flow controller provides 80 sccm of argon and 0.08 sccm of O₂ and the second flow controller provides 270 sccm of argon.

33. A process as in claim 28 wherein the non-reactive gas is in a range of 10 to 350 sccm and the oxygen-containing gas is in the range of 0.02 to 0.15 sccm.

34. A process as in claim 28 wherein the oxygen-containing gas is introduced into the process from the sputtering of a solid source of an oxygen-containing solid.

35. A process as in claim 28 wherein the oxygen-containing gas is introduced from control of leakage from the ambient.

36. A process as in claim 22 wherein the device is a magnetic junction memory device.

37. A process as in claim 22 further comprising the step of forming a bottom conductive layer under the insulation layer.

38. A process as in claim 22 wherein the insulating layer comprises aluminum oxide, magnesium oxide, or any insulating oxide.

39. A process as in claim 22 wherein the top conductive layer comprises a magnetic layer, part of an MRAM stack structure, or one or more layers of NiFe, CoFe, CoNiFe, and CoFeB.