Dynamic Range Adjusting Floating Point Execution Unit

• US 20100023568A1
• Filed: 07/22/2008
• Published: 01/28/2010
• Est. Priority Date: 07/22/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wait, Charles D., Muff, Adam J., Tubbs, Matthew R., Hickey, Mark J.
• Granted Patent: US 8,412,760 B2
• Time in Patent Office: Days
• US Class Current: 708/209
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value.

Claims

1. A circuit arrangement, comprising:

a register file including a plurality of registers configured to store 32-bit floating point values, each floating point value configured with a 1-bit sign field, an 8-bit exponent field and a 23-bit significand field, with the significand field including a 3-bit first portion and a 20-bit second portion;

a single precision floating point execution unit coupled to the register file and configured to process a first input floating point value stored in a first source register from the register file that is identified by a first floating point instruction being executed by the floating point execution unit to store a first output floating point value in a first destination register from the register file, and to process a second input floating point value stored in a second source register from the register file that is identified by a second floating point instruction being executed by the floating point execution unit to store a second output floating point value in a second destination register from the register file, wherein the floating point execution unit includes an exponent path and a significand path, wherein the first floating point instruction is a non-extended range floating point instruction and the second floating point instruction is an extended range floating point instruction, wherein the floating point execution unit is configured to execute the first floating point instruction by using data stored in the exponent field of the first input floating point value as an exponent and by concatenating data stored in the first and second portions of the significand field of the first input floating point value for use as a significand, and wherein the floating point execution unit is configured to execute the second floating point instruction by concatenating data stored in the exponent field and the first portion of the significand field of the second input floating point value for use as an exponent and by using data stored in the second portion of the significand field of the second input floating point value as a significand;

first shift logic coupled to in the significand path of the floating point execution unit and configured to receive input floating point values from the register file, the first shift logic configured to selectively shift data in the second portion of the significand field of the second input floating point value left three bits during execution of the second floating point instruction based upon the second floating point instruction being an extended range floating point instruction, the first shift logic further configured to pass unmodified the significand field of the first input floating point value based upon the first floating point instruction being a non-extended range floating point instruction; and

second shift logic coupled to the significand path of the floating point execution unit and configured to receive output floating point values from the floating point execution unit, the second shift logic configured to selectively shift data in the second portion of the significand field of the second output floating point value right three bits during execution of the second floating point instruction based upon the second floating point instruction being an extended range floating point instruction, the second shift logic further configured to pass unmodified the significand field of the first output floating point value based upon the first floating point instruction being a non-extended range floating point instruction; and

concatenation logic coupled to the exponent path of the floating point execution unit and configured to concatenate data from the exponent field and the first portion of the significand field of the second input floating point value during execution of the second floating point instruction based upon the second floating point instruction being an extended range floating point instruction.

2. A circuit arrangement, comprising:

an operand input configured to receive floating point operands, each floating point operand received by the operand input configured with an exponent field and a significand field, with the significand field including a first portion and a second portion; and

a floating point execution unit coupled to the operand input and configured to process floating point operands received by the operand input during execution of floating point instructions, wherein the floating point execution unit is configured to execute a first floating point instruction for which a first floating point operand has been received by the operand input by using data stored in the exponent field of the first floating point operand as an exponent and by concatenating data stored in the first and second portions of the significand field of the first floating point operand for use as a significand, and wherein the floating point execution unit is configured to execute a second floating point instruction for which a second floating point operand has been received by the operand input by concatenating data stored in the exponent field and the first portion of the significand field of the second floating point operand for use as an exponent and by using data stored in the second portion of the significand field of the second floating point operand as a significand.

3. The circuit arrangement of claim 2, wherein each floating point operand received by the operand input includes 32 bits and is configured to store a single precision floating point value, wherein each floating point operand includes a sign field having one bit, wherein the exponent field of each floating point operand has eight bits, wherein the first portion of the significand field of each floating point operand has three bits, and wherein the second portion of the significand field of each floating point operand has 20 bits.

4. The circuit arrangement of claim 2, further comprising a register file including a plurality of floating point registers, the register file including an output coupled to the operand input of the floating point execution unit, and an input coupled to receive a result output of the floating point execution unit.

5. The circuit arrangement of claim 4, wherein the floating point execution unit includes an exponent path and a significand path, wherein the floating point execution unit is configured to output a result floating point value at the result output, wherein the result floating point value is formatted in the same manner as each floating point operand such that the result floating point value includes an exponent field and a significand field, with the significand field including a first portion and a second portion, the circuit arrangement further comprising:

first shift logic disposed proximate a beginning of the significand path of the floating point execution unit and coupled to the operand input, the first shift logic configured to selectively shift data stored in the second portion of the significand field of the second floating point operand during execution of the second floating point instruction; and

second shift logic disposed proximate an end of the significand path of the floating point execution unit and configured to selectively shift data stored in the second portion of the significand field of the result floating point value during execution of the second floating point instruction, wherein the first and second shift logic shift the same number of bits but in opposite directions.

6. The circuit arrangement of claim 5, wherein the floating point execution unit includes logic coupled to the exponent path and configured to concatenate data in the exponent field and the first portion of the significand field of the second floating point operand during execution of the second floating point instruction.

7. The circuit arrangement of claim 2, wherein the first floating point instruction is of a non-range extended format, and wherein the second floating point instruction is of a range extended format.

8. The circuit arrangement of claim 7, wherein the second floating point instruction includes a mode bit set to identify the second floating point instruction as a range extended floating point instruction.

9. The circuit arrangement of claim 2, wherein the floating point execution unit is configured to execute the first floating point instruction when in a first mode and to execute the second floating point instruction when in a second mode.

10. The circuit arrangement of claim 9, wherein the floating point execution unit is configured to automatically switch from the first mode to the second mode in response to a number of overflow conditions meeting a threshold.

11. The circuit arrangement of claim 9, wherein the floating point execution unit is configured to switch between the first mode and the second mode based upon data stored in a special purpose register.

12. An integrated circuit device including the circuit arrangement of claim 2.

13. A program product comprising a computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 2.

21. The method of claim 12, wherein the floating point execution unit is configured to execute the first floating point instruction when in a first mode and to execute the second floating point instruction when in a second mode.

22. The method of claim 21, further comprising automatically switching the floating point execution unit from the first mode to the second mode in response to a number of overflow conditions meeting a threshold.

23. The method of claim 21, further comprising switching the floating point execution unit between the first mode and the second mode based upon data stored in a special purpose register.

14. A method of executing floating point instructions in a floating point execution unit, the method comprising:

receiving first and second floating point instructions, the first floating point instruction identifying a first floating point operand and the second floating point instruction identifying a second floating point operand, each of the first and second floating point operands configured with an exponent field and a significand field, with the significand field including a first portion and a second portion, wherein the exponent field, first portion of the significand field and second portion of the significand field in the first floating point operand are respectively mapped to the same bits as the exponent field, first portion of the significand field and second portion of the significand field in the second floating point operand;

executing the first floating point instruction in the floating point execution unit by using data stored in the exponent field of the first floating point operand as an exponent and by concatenating data stored in the first and second portions of the significand field of the first floating point operand for use as a significand; and

executing the second floating point instruction in the floating point execution unit by concatenating data stored in the exponent field and the first portion of the significand field of the second floating point operand for use as an exponent and by using data stored in the second portion of the significand field of the second floating point operand as a significand.

15. The method of claim 14, wherein each of the first and second floating point operands includes 32 bits and is configured to store a single precision floating point value, wherein each of the first and second floating point operands includes a sign field having one bit, wherein the exponent field of each of the first and second floating point operands has eight bits, wherein the first portion of the significand field of each of the first and second floating point operands has three bits, and wherein the second portion of the significand field of each of the first and second floating point operands has 20 bits.

16. The method of claim 14, wherein the first and second floating point values are respectively stored in first and second source floating point registers in a register file, the method further comprising storing first and second result floating point values generated by the floating point execution unit respectively during execution of the first and second floating point instructions in first and second destination floating point registers in the register file.

17. The method of claim 16, wherein the floating point execution unit includes an exponent path and a significand path, the method further comprising:

shifting data stored in the second portion of the significand field of the second floating point operand in a first direction within the significand path during execution of the second floating point instruction; and

shifting data stored in the second portion of the significand field of the second result floating point value within the significand path in a second direction that is opposite to the first direction during execution of the second floating point instruction.

18. The method of claim 17, further comprising concatenating data from the exponent field and the first portion of the significand field of the second floating point operand in the exponent path during execution of the second floating point instruction.

19. The method of claim 14, wherein the first floating point instruction is of a non-range extended format, and wherein the second floating point instruction is of a range extended format.

20. The method of claim 19, wherein the second floating point instruction includes a mode bit set to identify the second floating point instruction as a range extended floating point instruction.