Flash DIMM in a Standalone Cache Appliance System and Methodology

• US 20100023674A1
• Filed: 07/28/2008
• Published: 01/28/2010
• Est. Priority Date: 07/28/2008
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: Cache Iq
• Inventors: Aviles, Joaquin J.
• Granted Patent: US 7,941,591 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple page write and page program operations to different flash memory ranks, thereby improving write speeds to the flash DIMM cache memory.

Claims

1. A standalone cache unit for caching data operations requested from one or more networked data storage devices by one or more remote clients, the standalone cache unit comprising:

a flash dual in-line memory module (DIMM) cache memory for caching data that is requested by a remote client;

a packet processor coupled to the flash DIMM cache memory and to one or more I/O ports for transparently splicing connections between the data storage devices and remote clients, where the packet processor inspects network protocol traffic state parameters received on the I/O ports to determine if a request from a remote client can be serviced by the standalone cache unit; and

a cache control module for controlling caching operations in the flash DIMM cache memory.

2. The standalone cache unit of claim 1, where the flash DIMM cache memory comprises a multi-rank flash DIMM.

3. The standalone cache unit of claim 1, where the flash DIMM comprises a plurality of ranks of NAND flash memory devices.

4. The standalone cache unit of claim 1, where the flash DIMM comprises a plurality of ranks of NAND flash memory devices, where each rank comprises a plurality of 2 GB flash NAND memory devices.

5. The standalone cache unit of claim 1, where the flash DIMM comprises:

a first group of flash memory ranks with one or more associated first program registers for writing data to the first group of flash memory ranks, and

a second group of flash memory ranks with one or more associated second program registers for writing data to the second group of flash memory ranks.

6. The standalone cache unit of claim 5, where the cache control module is configured to sequentially load two or more data pages to the one or more associated first program registers while two or more additional data pages are programmed into the second group of flash memory ranks from the one or more associated second program registers.

7. The standalone cache unit of claim 1, where the cache control module configured to pipeline multiple page write and page program operations to different memory ranks in the flash DIMM cache memory.

8. The standalone cache unit of claim 1, where the cache controller comprises a page cache for sequentially transferring multiple data pages to program registers in two or more memory ranks in the flash DIMM cache memory while data pages that were previously transferred to program registers in other memory ranks in the flash DIMM cache memory are simultaneously being programmed.

9. The standalone cache unit of claim 1, where the packet processor executes software that transparently monitors NFS and CIFS traffic between remote clients and NAS subsystems.

10. A method for controlling data write operations to a multi-rank flash memory module, comprising:

programming in parallel at least two data pages into a first group of memory ranks of flash memory chips in the multi-rank flash memory module, where the at least two data pages were previously loaded into a first group of program registers associated with the first group of memory ranks; and

loading at least two additional data pages to a second group of program registers associated with a second group of memory ranks of flash memory chips in the multi-rank flash memory module while programming in parallel the at least two data pages into the first group of memory ranks.

11. The method of claim 10, where loading at least two additional data pages comprises:

loading a first data page to a first program register located in a first memory rank in the multi-rank flash memory module, and then

loading a second data page to a second program register located in a second memory rank in the multi-rank flash memory module,

where the first and second data page are loaded while programming in parallel the at least two data pages into the first group of memory ranks.

12. The method of claim 11, where programming in parallel at least two data pages comprises simultaneously programming a third memory rank and a fourth memory rank in the multi-rank memory module with a third data page and a fourth data page, respectively, so as to overlap with the loading the first data page and second data page.

13. The method of claim 10, where programming in parallel at least two data pages comprises programming in parallel at least two data pages into a first group of memory ranks in a multi-rank flash cache memory module.

14. The method of claim 10, where loading at least two additional data pages comprises sequentially loading the at least two additional data pages from a page cache in a cache controller to the second group of program registers associated with the second group of memory ranks a multi-rank flash cache memory module.

15. The method of claim 10, where the data write operations comprise data write operations to a multi-rank flash dual in-line memory module (DIMM).

16. A method for caching data operations, comprising:

receiving at a standalone cache unit a request from a remote client to perform a specified data operation at one or more networked data storage devices;

inspecting packet parameters in one or more TCP/IP stack layers associated with the request to determine if the request can be serviced by a flash dual in-line memory module (DIMM) cache memory located at the standalone cache unit; and

performing the specified data operation at the DIMM cache memory if the request can be serviced by the standalone cache unit.

17. The method of claim 16, where performing the specified data operation at the DIMM cache memory comprises reading data specified by the request from the DIMM cache memory.

18. The method of claim 16, where performing the specified data operation at the DIMM cache memory comprises writing data specified by the request to the DIMM cache memory.

19. The method of claim 18, where writing data specified by the request comprises:

programming in parallel at least two data pages into a first group of memory ranks in the DIMM cache memory, where the at least two data pages were previously loaded into a first group of program registers associated with the first group of memory ranks; and

loading at least two additional data pages to a second group of program registers associated with a second group of memory ranks in the DIMM cache memory while programming in parallel the at least two data pages into the first group of memory ranks.

20. The method of claim 16, where performing the specified data operation at the DIMM cache memory comprises sequentially transferring multiple data pages to two or more memory ranks in the flash DIMM cache memory while simultaneously programming additional data pages to other flash memory ranks in the flash DIMM cache memory.