OPTIMIZING NON-PREEMPTIBLE READ-COPY UPDATE FOR LOW-POWER USAGE BY AVOIDING UNNECESSARY WAKEUPS

• US 20100023732A1
• Filed: 07/24/2008
• Published: 01/28/2010
• Est. Priority Date: 07/24/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Triplett, Joshua A.
• Granted Patent: US 8,108,696 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A technique for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers. A grace period processing action is implemented that requires a processor that may be running a non-preemptible reader of the shared data element to pass through a quiescent state before further grace period processing can proceed. A power status of the processor is also determined. Further grace period processing may proceed without requiring the processor to pass through a quiescent state if the power status indicates that quiescent state processing by the processor is unnecessary.

Claims

1. A method for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:

implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing;

determining a power status of said processor; and

proceeding with said further grace period processing without requiring said processor to pass through said quiescent state if said power status indicates that quiescent state processing by said processor is unnecessary.

2. A method in accordance with claim 1, wherein said power status comprises said processor being in either a non-low-power state or a low-power state.

3. A method in accordance with claim 2, wherein said low-power state includes said processor being in a dynamic tick timer mode.

4. A method in accordance with claim 1, wherein said power status is determined by a current power state of said processor and said processor is designated as having passed through said quiescent state if said current power state is a low-power state.

5. A method in accordance with claim 1, wherein said power status is determined from a power status indicator that is manipulated by said processor when said processor enters or leaves a low-power state.

6. A method in accordance with claim 1, wherein said further grace period processing comprises one or more of freeing said shared data element, processing a callback that frees said shared data element, or changing a mode of operation determined by said shared data element.

7. A system adapted for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:

one or more processors;

a memory coupled to said one or more processors, said memory including a computer useable medium tangibly embodying at least one program of instructions executable by said processor to perform operations, comprising;

implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing;

determining a power status of said processor; and

proceeding with said further grace period processing without requiring said processor to pass through said quiescent state if said power status indicates that quiescent state processing by said processor is unnecessary.

8. A system in accordance with claim 7, wherein said power status comprises said processor being in either a non-low-power state or a low-power state.

9. A system in accordance with claim 8, wherein said low-power state includes said processor being in a dynamic tick timer mode.

10. A system in accordance with claim 7, wherein said power status is determined by a current power state of said processor and said processor is designated as having passed through said quiescent state if said current power state is a low-power state.

11. A system in accordance with claim 7, wherein said power status is determined from a power status indicator that is manipulated by said processor when said processor enters or leaves a low-power state.

12. A system in accordance with claim 7, wherein said further grace period processing comprises one or more of freeing said shared data element, processing a callback that frees said shared data element, or changing a mode of operation determined by said shared data element.

13. A computer program product for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:

one or more machine-useable media;

logic provided by said one or more media for programming a data processing platform to operate as by;

implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing;

determining a power status of said processor; and

proceeding with said further grace period processing without requiring said processor to pass through said quiescent state if said power status indicates that quiescent state processing by said processor is unnecessary.

14. A computer program product in accordance with claim 13, wherein said power status comprises said processor being in either a non-low-power state or a low-power state.

15. A computer program product in accordance with claim 14, wherein said low-power state includes said processor being in a dynamic tick timer mode.

16. A computer program product in accordance with claim 13, wherein said power status is determined by a current power state of said processor and said processor is designated as having passed through said quiescent state if said current power state is a low-power state.

17. A computer program product in accordance with claim 13, wherein said power status is determined from a power status indicator that is manipulated by said processor when said processor enters or leaves a low-power state.

18. A computer program product in accordance with claim 13, wherein said further grace period processing comprises one or more of freeing said shared data element, processing a callback that frees said shared data element, or changing a mode of operation determined by said shared data element.

19. A computer program product for low-power detection of a grace period following a shared data element update that affects non-preemptible data readers, comprising:

one or more machine-useable media;

logic provided by said one or more media for programming a data processing platform to operate as by;

implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing;

determining a power status of said processor; and

proceeding with said further grace period processing without requiring said processor to pass through said quiescent state if said power status indicates that quiescent state processing by said processor is unnecessary;

said power status comprising said processor being in either a non-low-power state or a low-power state;

said low-power state including said processor being in a dynamic tick timer mode;

said power status is determined by a current power state of said processor and said processor is designated as having passed through said quiescent state if said current power state is a low-power state; and

said power status being determined from a power status indicator that is manipulated by said processor when said processor enters or leaves a low-power state.

20. A computer program product in accordance with claim 19, wherein said further grace period processing comprises one or more of freeing said shared data element, processing a callback that frees said shared data element, or changing a mode of operation determined by said shared data element.