SOFT ERROR CORRECTION METHOD, MEMORY CONTROL APPARATUS AND MEMORY SYSTEM

• US 20100023827A1
• Filed: 10/05/2009
• Published: 01/28/2010
• Est. Priority Date: 03/17/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: HONDA, Yasufumi, KOGUCHI, Takashi, SUZUKI, Kenji
• Granted Patent: US 8,365,031 B2
• Time in Patent Office: Days
• US Class Current: 714/747
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Claims

1. A soft error correction method for a memory system having n memory access controllers that are configured to access n memories for storing byte-sliced data in cycle synchronism, and a system controller that is configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, comprising:

when a correctable error is detected in data read from one of the memories, holding an error generation and an error address where the error was detected within a corresponding one of the memory access controllers; and

responsive to the error generation, reading the data from the error address of the corresponding one of the memories, correcting the error and rewriting corrected data to the error address by the one of the memory access controllers holding the error address from the system controller, periodically or when an idle state continues for a predetermined time, without intervention from the MPUs.

2. A memory control apparatus for a memory system having n memory access controllers that are configured to access n memories for storing byte-sliced data in cycle synchronism, and a system controller that is configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, comprising:

a part configured to hold an error address where a correctable error is detected within a corresponding one of the memory access controllers, when the correctable error is detected in data read from one of the memories, and to make an error notification with respect to the system controller from the corresponding one of the memory access controllers; and

a part, responsive to the error notification, configured to control the one of the memory access controllers holding the error address from the system controller without intervention from the MPUs, to read the data from the error address of the corresponding one of the memories, to correct the error and to rewrite corrected data to the error address.

3. The memory control apparatus as claimed in claim 2, wherein the error address is once sent to the system controller, instead of holding the error address where the error was detected within the corresponding one of the memory access controllers, so that an error correction command and the error address are simultaneously input to each of the memory access controllers from the system controller.

4. The memory control apparatus as claimed in claim 2, wherein responsive to the error notification, arbitrary memory access controllers not holding the error address are controlled from the system controller, data is read from a preset address of memories corresponding to the arbitrary memory access controllers, and a timing adjustment is thereafter performed by waiting for a time it would take to carry out a write back.

5. The memory control apparatus as claimed in claim 2, further comprising:

a part, responsive to the error notification, configured to control arbitrary memory access controllers not holding the error address from the system controller, and to read data from a preset dummy read address of memories corresponding to the arbitrary memory access controllers and to write back the data as it is to the preset dummy read address.

6. The memory control apparatus as claimed in claim 5, further comprising:

a part, responsive to the error notification, configured to input an error correction command and the dummy read address to each of the memory access controllers from the system controller.

7. The memory control apparatus as claimed in claim 2, wherein the error notification is made using a bus that is configured to send a status from the system controller to the one of the memory access controllers.

8. A memory control apparatus for a memory system having n memory access controllers that are configured to access n memories for storing byte-sliced data in cycle synchronism, and a system controller that is configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, comprising:

a part configured to hold an error generation and an error address where a correctable error is detected within a corresponding one of the memory access controllers, when the correctable error is detected in data read from one of the memories; and

a part, responsive to the error generation, configured to read the data from the error address of the corresponding one of the memories, to correct the error and rewrite corrected data to the error address by the one of the memory access controllers holding the error address from the system controller, periodically or when an idle state continues for a predetermined time, without intervention from the MPUs.

9. A memory system comprising:

n memory access controllers configured to access n memories for storing byte-sliced data in cycle synchronism; and

a system controller configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, wherein;

when a correctable error is detected in data read from one of the memories, an error address where the error was detected is held within a corresponding one of the memory access controllers, and an error notification is made with respect to the system controller from the corresponding one of the memory access controllers; and

responsive to the error notification, the one of the memory access controllers holding the error address is controlled from the system controller without intervention from the MPUs, the data from the error address of the corresponding one of the memories is read, the error is corrected and corrected data is rewritten to the error address.

10. The memory system as claimed in claim 9, wherein the error address is once sent to the system controller, instead of holding the error address where the error was detected within the corresponding one of the memory access controllers, so that an error correction command and the error address are simultaneously input to each of the memory access controllers from the system controller.

11. The memory system as claimed in claim 9, wherein responsive to the error notification, arbitrary memory access controllers not holding the error address are controlled from the system controller, data is read from a preset address of memories corresponding to the arbitrary memory access controllers, and a timing adjustment is thereafter performed by waiting for a time it would take to carry out a write back.

12. The memory system as claimed in claim 9, wherein responsive to the error notification, arbitrary memory access controllers not holding the error address are controlled from the system controller, data is read from a preset dummy read address of memories corresponding to the arbitrary memory access controllers and written back as it is to the preset dummy read address.

13. The memory system as claimed in claim 12, wherein responsive to the error notification, an error correction command and the dummy read address are input to each of the memory access controllers from the system controller.

14. The memory system as claimed in claim 9, wherein the error notification is made using a bus that is configured to send a status from the system controller to the one of the memory access controllers.

15. A memory system comprising:

n memory access controllers configured to access n memories for storing byte-sliced data in cycle synchronism; and

a system controller configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, wherein;

when a correctable error is detected in data read from one of the memories, an error generation and an error address where the error was detected are held within a corresponding one of the memory access controllers; and

responsive to the error generation, the data is read from the error address of the corresponding one of the memories, the error is corrected and corrected data is rewritten to the error address by the one of the memory access controllers holding the error address from the system controller, periodically or when an idle state continues for a predetermined time, without intervention from the MPUs.

16. A soft error correction method for a memory system having n memory access controllers that are configured to access n memories for storing byte-sliced data in cycle synchronism, a system controller that is configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, and a crossbar switch that is configured to switch data between the memory access controllers and the MPUs, where m and n are integers greater than or equal to two, comprising:

when a correctable error is detected in data read from one of the memories, an error notification and an error address where the error was detected are sent from a corresponding one of the memory access controllers to the system controller; and

responsive to the error notification, sending the error address where the error was detected from the system controller to the corresponding one of the memory access controllers without intervention from the MPUs, to control the corresponding one of the memory access controllers to read the data from the error address, correct the error and rewrite corrected data to the error address.