Product Optimization Process for Embedded Passives

• US 20100024210A1
• Filed: 07/31/2007
• Published: 02/04/2010
• Est. Priority Date: 07/31/2007
• Status: Abandoned Application

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Bendix, Lendon L.
• Application Number:
  US11/830,940
• Publication Number:
  US 20100024210A1
• Time in Patent Office: Days
• US Class Current: 29/832
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2203/171 Tuning, e.g. by trimming of printed components or high frequency circuits
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/46 Manufacturing multilayer circuits
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method is provided for manufacturing a multi-layer circuit board having embedded passive components. The method includes selectively removing portions of at least one layer of the multi-layer circuit board (300) to form a two dimensional array of test points (304) defining a grid extending across a surface of the multi-layer circuit board in those areas on which a circuit is to be formed. The method also includes measuring at each of the test points at least one electrical parameter which is useful for defining a characteristic of the multi-layer circuit board. The method further includes selectively modifying the geometry of at least one embedded passive component to be formed on the multi-layer circuit board based on an analysis of a result obtained in the measuring step.

Claims

1. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:

selectively removing portions of at least one layer of a multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed;

measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of the multi-layer circuit board;

selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on an analysis of a result obtained in said measuring step.

2. The method according to claim 1, further comprising selecting said at least one layer to comprise a conductive metal layer.

3. The method according to claim 2, further comprising selecting said multi-layer circuit board to include a dielectric layer and a passive material layer disposed between said conductive metal layer and said dielectric layer.

4. The method according to claim 2, further comprising forming each said test point by removing a portion of said conductive metal layer to isolate a center contact from a remaining portion of said conductive metal layer.

5. the method according to claim 4, further comprising selecting said portion to have an annular profile which is coaxial with said center contact.

6. The method according to claim 1, further comprising forming said at least one embedded passive component on said multi-layer circuit board using said geometry which has been modified.

7. The method according to claim 1, further comprising selecting said analysis to include a neural analysis.

8. The method according to claim 7, further comprising determining a system identification for the multi-layer circuit board using said neural analysis.

9. The method according to claim 1, further comprising selecting said electrical parameter from the group comprising a resistance, an impedance, and a capacitance.

10. The method according to claim 1, wherein said two dimensional array of test points is a linear two-dimensional array forming an x, y grid.

11. The method according to claim 1, further comprising modifying a pattern formed by said two-dimensional array at selected locations to align a location of at least one test point with a location of said multi-layer circuit board where a via will be placed.

12. The method according to claim 11, further comprising performing a second measuring step at each test point of said test points aligned with said vias to re-measure a value of said at least one electrical parameter at said test points which is useful for defining said characteristic of said multi-layer circuit board, said second measuring step performed after at least a portion of a circuit has been formed on said multi-layer circuit board.

13. The method according to claim 12, further comprising repeating said analysis step using measurement data acquired in said second measuring step.

14. The method according to claim 1, further comprising excluding said test points from selected areas of said multi-layer circuit board where an embedded passive component or circuit trace will be placed in a subsequent processing step.

15. The method according to claim 1, further comprising performing an etching process to form said two dimensional array of test points on said multi-layer circuit board.

16. The method according to claim 1, further comprising repeating said measuring and said analyzing step for each one of a plurality of multi-layer circuit boards to be manufactured with a particular embedded circuit design.

17. The method according to claim 16, further comprising improving an accuracy of said analysis with each repetition of said analyzing step by using in each analysis step measurement results from a plurality of said measurements of said plurality of multi-layer circuit boards.

18. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:

selectively removing portions of at least one layer of a multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed;

measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of said multi-layer circuit board;

performing a neural analysis of said multi-layer circuit board using data obtained from said measuring step; and

selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on said neural analysis.

19. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:

selectively removing portions of at least one layer of the multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed;

measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of said multi-layer circuit board;

performing a neural analysis of said multi-layer circuit board using data obtained from said measuring step;

selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on said neural analysis; and

forming said at least one embedded passive component on said multi-layer circuit board using said geometry which has been modified.

20. The method according to claim 19, further comprising selecting said multi-layer circuit board to include a dielectric layer, a conductive metal layer, and a passive material layer disposed between said dielectric layer and said conductive metal layer.

21. The method according to claim 20, further comprising forming each said test point by removing a portion of said conductive metal layer to isolate a center contact from a remaining portion of said conductive metal layer.