Product Optimization Process for Embedded Passives
First Claim
1. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:
- selectively removing portions of at least one layer of a multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed;
measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of the multi-layer circuit board;
selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on an analysis of a result obtained in said measuring step.
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Accused Products
Abstract
A method is provided for manufacturing a multi-layer circuit board having embedded passive components. The method includes selectively removing portions of at least one layer of the multi-layer circuit board (300) to form a two dimensional array of test points (304) defining a grid extending across a surface of the multi-layer circuit board in those areas on which a circuit is to be formed. The method also includes measuring at each of the test points at least one electrical parameter which is useful for defining a characteristic of the multi-layer circuit board. The method further includes selectively modifying the geometry of at least one embedded passive component to be formed on the multi-layer circuit board based on an analysis of a result obtained in the measuring step.
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Citations
21 Claims
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1. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:
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selectively removing portions of at least one layer of a multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed; measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of the multi-layer circuit board; selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on an analysis of a result obtained in said measuring step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:
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selectively removing portions of at least one layer of a multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed; measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of said multi-layer circuit board; performing a neural analysis of said multi-layer circuit board using data obtained from said measuring step; and selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on said neural analysis.
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19. A method for manufacturing a multi-layer circuit board having embedded passive components, comprising:
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selectively removing portions of at least one layer of the multi-layer circuit board to form a two dimensional array of test points defining a grid extending across a surface of said multi-layer circuit board in those areas on which a circuit is to be formed; measuring at each test point of said test points at least one electrical parameter which is useful for defining a characteristic of said multi-layer circuit board; performing a neural analysis of said multi-layer circuit board using data obtained from said measuring step; selectively modifying a geometry of at least one embedded passive component to be formed on said multi-layer circuit board based on said neural analysis; and forming said at least one embedded passive component on said multi-layer circuit board using said geometry which has been modified. - View Dependent Claims (20, 21)
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Specification