SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100025675A1
• Filed: 07/29/2009
• Published: 02/04/2010
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, YAMAZAKI, Shunpei, MIYAIRI, Hidekazu, SHIRAISHI, Kojiro
• Granted Patent: US 8,293,595 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/10 OLED displays
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/8722 : Peripheral sealing arrangements, e.g. adhesives, sealants

Abstract

In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

a first insulating film over the gate electrode;

an oxide semiconductor layer over the first insulating film;

a second insulating film over the oxide semiconductor layer; and

a conductive film over the oxide semiconductor layer,

wherein a first region in which the oxide semiconductor layer and the second insulating film are contact with each other overlaps with at least part of the gate electrode, and

wherein a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the conductive film are in contact with each other is smaller than a thickness of the oxide semiconductor layer in the first region.

2. The semiconductor device according to claim 1, wherein part of the conductive film is formed over the second insulating film.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least In, Ga and Zn.

4. The semiconductor device according to claim 1, wherein the first insulating film is one of a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an aluminum nitride film and an yttrium oxide film.

5. The semiconductor device according to claim 1, wherein the second insulating film is one of a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an aluminum nitride film and an yttrium oxide film.

6. The semiconductor device according to claim 1, wherein the first insulating film includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

7. The semiconductor device according to claim 1, wherein the second insulating film includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

8. The semiconductor device according to claim 1, wherein the conductive film is a stacked film including a titanium film and an aluminum film.

9. The semiconductor device according to claim 1, further comprising a silicon nitride film or a silicon nitride oxide film between the gate electrode and the first insulating film.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a stacked layer in which a first insulating film is formed over the gate electrode, an oxide semiconductor layer is formed over the first insulating film, and a second insulating film is formed over the oxide semiconductor layer by sputtering without being exposed to air;

forming a protective film in a region overlapping with the gate electrode by selectively etching the second insulating film;

etching an upper layer of the oxide semiconductor layer with the protective film as a mask;

forming a conductive film over the oxide semiconductor layer and the protective film; and

selectively etching the conductive film with the protective film used as an etching stopper.

11. The method according to claim 10, wherein the first insulating film, the oxide semiconductor layer and the second insulating film are formed in the same chamber.

12. The method according to claim 10, wherein the first insulating film is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.

13. The method according to claim 10, wherein the oxide semiconductor layer is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.

14. The method according to claim 10, wherein the second insulating film is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a stacked layer in which a first insulating film is formed over the gate electrode, an oxide semiconductor layer is formed over the first insulating film, and a second insulating film is formed over the oxide semiconductor layer by sputtering without being exposed to air;

forming a protective film in a region overlapping with the gate electrode by selectively etching the second insulating film;

etching an upper layer of the oxide semiconductor layer with the protective film as a mask;

forming a conductive film over the oxide semiconductor layer and the protective film; and

selectively etching the conductive film with the protective film used as an etching stopper,

wherein the first insulating film and the oxide semiconductor layer are formed in the same chamber.

16. The method according to claim 15, wherein the first insulating film, the oxide semiconductor layer and the second insulating film are formed in the same chamber.

17. The method according to claim 15, wherein the first insulating film is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.

18. The method according to claim 15, wherein the oxide semiconductor layer is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.

19. The method according to claim 15, wherein the second insulating film is formed under an atmosphere including only oxygen or an atmosphere including oxygen at 90% or more and an inert gas at 10% or less by a sputtering method.