Interface device for wireless testing, semiconductor device and semiconductor package including the same, and method for wirelessly testing using the same

• US 20100025682A1
• Filed: 08/03/2009
• Published: 02/04/2010
• Est. Priority Date: 08/04/2008
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: An, Young-Soo, Lee, Sang-Hoon, Cho, Chang-Hyun, Oh, Se-Jang, Byun, Eun-Jo
• Application Number:
  US12/462,373
• Publication Number:
  US 20100025682A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In an interface device for wireless testing capable of testing a semiconductor chip in a non-contact manner, a semiconductor device and a semiconductor package including the same, and a method for wirelessly testing a semiconductor device using the same are provided, the interface device for wireless testing includes an interface substrate, interface antennas on the interface substrate, and interface transmitting and receiving circuits on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to input/output pads of a semiconductor chip via interface vias passing through the interface substrate.

Claims

1. An interface device for wireless testing comprising:

an interface substrate;

coil shaped interface antennas on the interface substrate; and

interface transmitting and receiving circuits on the interface substrate electrically connected to the interface antennas via interface interconnections on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to input/output pads of a semiconductor chip via interface vias passing through the interface substrate.

2. The interface device according to claim 1, wherein the interface substrate comprises an insulating hard substrate, the insulating hard substrate being one of a printed circuit board (PCB) substrate, a plastic substrate, a glass substrate, and a ceramic substrate.

3. The interface device according to claim 1, wherein the interface device is a redistribution structure formed on the wafer.

4. The interface device according to claim 1, wherein the interface substrate comprises at least two layers comprising an upper interface substrate and a lower interface substrate.

5. The interface device according to claim 4, wherein the interface vias comprise upper interface vias passing through the upper interface substrate, and lower interface vias passing through the lower interface substrate.

6. The interface device according to claim 5, wherein the interface antennas are disposed on the upper interface substrate and the interface transmitting and receiving circuits are disposed on the lower interface substrate.

7. The interface device according to claim 6, wherein the upper interface vias electrically connect the interface antennas to the interface transmitting and receiving circuits, and the lower interface vias electrically connect the interface transmitting and receiving circuits to the input/output pads of the semiconductor chip.

8. The interface device according to claim 1, further comprising interface pads disposed between the interface transmitting and receiving circuits and the input/output pads of the semiconductor chip, for electrically connecting the interface transmitting and receiving circuits to the input/output pads of the semiconductor chip.

9. The interface device according to claim 1, wherein the input/output pads of the semiconductor chip are disposed in a central region on an upper surface of the semiconductor chip, and wherein the interface antennas are disposed in a region corresponding to outer edges of the interface substrate.

10. A semiconductor device comprising:

a semiconductor chip at a wafer level;

input/output pads on the semiconductor chip; and

an interface device for wireless testing on the semiconductor chip,

wherein the interface device comprises;

an interface substrate;

interface antennas on the interface substrate; and

interface transmitting and receiving circuits on the interface substrate electrically connected to the interface antennas via interface interconnections on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to the input/output pads of the semiconductor chip via interface vias, and the interface vias pass through the interface substrates.

11. The semiconductor device according to claim 10, wherein the interface substrate comprises an insulating hard substrate, the insulating hard substrate being one of a PCB substrate, a plastic substrate, a glass substrate, a polymer substrate, and a ceramic substrate, wherein each interface antenna comprises a polygonal or circular coil, and wherein each interface transmitting and receiving circuit comprises a transmitting circuit and a receiving circuit that in turn comprise resistors, capacitors and transistors.

12. The semiconductor device according to claim 10, wherein the interface substrate comprises at least two layers comprising an upper interface substrate and a lower interface substrate, and wherein the interface antennas are disposed on the upper interface substrate and the interface transmitting and receiving circuits are disposed on the lower interface substrate.

13. The semiconductor device according to claim 12, wherein the interface vias comprise:

upper interface vias passing through the upper interface substrates for electrically connecting the interface antennas to the interface transmitting and receiving circuits; and

lower interface vias passing through the lower interface substrates for electrically connecting the interface transmitting and receiving circuits to the input/output pads of the semiconductor chip.

14. The interface device according to claim 10, wherein the interface device is a redistribution structure formed on an upper part of the wafer.

15. A semiconductor package comprising:

a semiconductor chip;

input/output pads on the semiconductor chip; and

an interface device for wireless testing formed on the semiconductor chip,

wherein the interface device comprises;

an interface substrate;

interface antennas on the interface substrate; and

interface transmitting and receiving circuits on the interface substrate electrically connected to the interface antennas via interface interconnections on the interface substrate, wherein the interface antennas are electrically connected to the input/output pins via bonding wires.

16. The semiconductor package according to claim 15, wherein the interface substrate comprises at least two layers comprising an upper interface substrate and a lower interface substrate, and wherein the interface antennas are disposed on the upper interface substrate and the interface transmitting and receiving circuits are disposed on the lower interface substrate.

17. The semiconductor package according to claim 16, further comprising upper interface vias passing through the upper interface substrates for electrically connecting the interface antennas to the interface transmitting and receiving circuits.

18. A semiconductor package comprising:

a semiconductor chip;

input/output pads on the semiconductor chip; and

an interface device for wireless testing formed on the semiconductor chip,

wherein the interface device comprises;

an interface substrate;

interface antennas on the interface substrate; and

interface transmitting and receiving circuits on the interface substrate electrically connected to the interface antennas via interface interconnections on the interface substrate, wherein the interface antennas are electrically connected to external solder balls via bumps.

19. The semiconductor package according to claim 18, wherein the interface substrate comprises at least two layers comprising an upper interface substrate and a lower interface substrate, and wherein the interface antennas are disposed on the upper interface substrate and the interface transmitting and receiving circuits are disposed on the lower interface substrate.

20. The semiconductor package according to claim 19, further comprising upper interface vias passing through the upper interface substrates for electrically connecting the interface antennas to the interface transmitting and receiving circuits.