Lateral Devices Containing Permanent Charge

• US 20100025726A1
• Filed: 04/30/2009
• Published: 02/04/2010
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Paul, Amit, Darwish, Mohamed N.
• Granted Patent: US 8,330,186 B2
• Time in Patent Office: Days
• US Class Current: 257/141
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.

Claims

1. A lateral semiconductor device comprising:

a body region connected to a drain region by a drift region; and

permanent charge, sufficient to cause depletion in at least a portion of said drift layer at the interface between the drift layer and an insulation region.

2. The lateral semiconductor device of claim 1, wherein said drift region is formed as a well.

3. The lateral semiconductor device of claim 1, further comprising a buried region within said drift region.

4. The lateral semiconductor device of claim 1, further comprising a trench gate.

5. The lateral semiconductor device of claim 4, wherein said trench gate is interposed between said source region and said drain region.

6. The lateral semiconductor device of claim 5, wherein said trench gate extends laterally above a silicon surface.

7. The lateral semiconductor device of claim 5, further comprising a gate dielectric surrounding said trench gate, and having a thickness, adjoining said body region, which is less than its thickness adjoining said drift region.

8. The lateral semiconductor device of claim 1, further comprising an insulation region overlying said drift region between said body region and said drain region;

and wherein said permanent charge is embedded within said insulation region.

9-19. -19. (canceled)

20. A lateral semiconductor device comprising:

a carrier source;

a semiconductor drift region laterally interposed between said carrier source and a drain region; and

permanent charge, embedded in at least one insulating region which vertically adjoins said drift region, which balances charge in said drift region when said drift region is depleted.

21. The lateral semiconductor device of claim 20, wherein said carrier source comprises a first-conductivity type source diffusion, and a second-conductivity type channel region which is interposed between said source diffusion and said drift region.

22. The lateral semiconductor device of claim 20, wherein carrier emission from said carrier source is controlled by voltages applied on a control gate.

24. The lateral semiconductor device of claim 20, wherein said drift region is formed as a well.

25. The lateral semiconductor device of claim 20, further comprising a buried region within said drift region.

26. The lateral semiconductor device of claim 20, further comprising a trench gate.

27. The lateral semiconductor device of claim 26, wherein said trench gate is between said source region and said drain region.

28. The lateral semiconductor device of claim 26, wherein said trench gate extends laterally into said insulation region.

29. The lateral semiconductor device of claim 25, further comprising a second buried region.

23. (canceled)

30-33. -33. (canceled)

34. A method of increasing depletion in a drift layer of a lateral semiconductor device comprising:

providing an insulation region in contact with said drift layer;

effecting charge balancing by use of permanent charge positioned within said insulation.

35. The method of claim 34, wherein said permanent charge is positioned in said insulation region at an interface with said drift layer.

36. The method of claim 34, further comprising providing a surface layer within said drift layer.

37-38. -38. (canceled)