SEMICONDUCTOR DEVICE

• US 20100025760A1
• Filed: 07/09/2009
• Published: 02/04/2010
• Est. Priority Date: 07/31/2008
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: KAWASHIMA, Yoshiya
• Application Number:
  US12/499,813
• Publication Number:
  US 20100025760A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a MOSFET cell having a super junction structure and a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell. The MOSFET cell includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate, a gate electrode and a first column region of a second conductivity type formed in the epitaxial layer, a first base region of the second conductivity type formed on a surface of the epitaxial layer, and a source region of the first conductivity type formed on a surface of the first base region. The diode cell includes a second column region of the second conductivity type formed in the epitaxial layer and having a larger width than the first column region, and a second base region of the second conductivity type formed on the surface of the epitaxial layer.

Claims

1. A semiconductor device comprising:

a metal-oxide semiconductor field-effect transistor (MOSFET) cell having a super junction structure; and

a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell, wherein

the MOSFET cell includes;

an epitaxial layer of a first conductivity type formed on a semiconductor substrate,

a gate electrode formed in a trench of the epitaxial layer with an insulating layer interposed therebetween,

a first column region of a second conductivity type formed in the epitaxial layer,

a first base region of the second conductivity type formed on a surface of the epitaxial layer, and

a source region of the first conductivity type formed on a surface of the first base region, and

the diode cell includes;

a second column region of the second conductivity type formed in the epitaxial layer, the second column region having a larger width than the first column region, and

a second base region of the second conductivity type formed on the surface of the epitaxial layer.

2. The semiconductor device according to claim 1, wherein the gate electrode is further formed in the diode cell with the same layout as in the MOSFET cell.

3. The semiconductor device according to claim 2, wherein the gate electrode is placed respectively on periphery of the first column region and the second column region in a plan view.

4. The semiconductor device according to claim 1, wherein the source region is formed only in the MOSFET cell.

5. The semiconductor device according to claim 1, wherein a breakdown voltage of the diode cell is smaller than a breakdown voltage of the MOSFET cell.

6. The semiconductor device according to claim 1, wherein the super junction structure is formed by the epitaxial layer and the first column region.

7. The semiconductor device according to claim 1, further comprising:

an element formation area where the MOSFET cell is placed; and

a peripheral area located outside of the element formation area and having an element separation region,

wherein the diode cell is placed in substitution for a part of the MOSFET cell arranged regularly in the element formation area.

8. The semiconductor device according -to claim 7, wherein the diode cell is arranged periodically or randomly in the element formation area.

9. The semiconductor device according to claim 7, wherein the diode cell is placed on a boundary of the element formation area with the peripheral area.

10. The semiconductor device according to claim 9, wherein the diode cell is arranged along the peripheral area.

11. The semiconductor device according to claim 10, wherein the diode cell is placed in a plurality of rows.