TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SUCH A TRANSISTOR DEVICE

• US 20100025766A1
• Filed: 12/10/2007
• Published: 02/04/2010
• Est. Priority Date: 12/15/2006
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Nuttinck, Sebastien, Curatola, Gilberto
• Granted Patent: US 8,362,561 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.

Claims

1. A transistor device, the transistor device comprising

a substrate;

a fin extending along a horizontal direction on the substrate;

a first source/drain region of a first type of conductivity in the fin;

a second source/drain region of a second type of conductivity in the fin, wherein the first type of conductivity differs from the second type of conductivity;

a channel region in the fin between the first source/drain region and the second source/drain region;

a gate insulator on the channel region;

a gate structure on the gate insulator;

wherein, in the horizontal direction, the channel region extends between the first source/drain region and the second source/drain region.

2. The transistor device according to claim 1, wherein the first type of conductivity is opposite to the second type of conductivity.

3. The transistor device according to claim 1, adapted as a semiconductor transistor device, particularly as a CMOS transistor device.

4. The transistor device according to claim 1, wherein the gate structure is a double gate structure.

5. The transistor device according to claim 4, wherein the double gate structure comprises a first gate portion located at least partially along a first vertical surface of the gate insulator and comprises a second gate portion located at least partially along a second vertical surface of the gate insulator.

6. The transistor device according to claim 5, wherein a material of the first gate portion differs from a material of the second gate portion.

7. The transistor device according to claim 5, wherein a work function of the material of the first gate portion is adapted to provide a characteristic of an N-type tunneling field effect transistor and a work function of the material of the second gate portion is adapted to provide a characteristic of a P-type tunneling field effect transistor.

8. The transistor device according to claim 5, wherein at least one of the group consisting of the first gate portion and the second gate portion is located partially along a horizontal surface of the gate insulator.

9. The transistor device according to claim 1, wherein the channel region is an intrinsic portion of a semiconductor material of which the fin is made.

10. The transistor device according to claim 1, formed as one of the group consisting of a logic circuit and a memory circuit.

11. The transistor device according to claim 1, wherein the first source/drain region and the second source/drain region are located at the same height level in the horizontal direction.

12. The transistor device according to claim 1, wherein the channel region, the first source/drain region and the second source/drain region are laterally neighbored along the horizontal direction.

16. The method according to claim 11, wherein a first gate portion of the gate structure is selectively formed extending at least partially along a first vertical surface of the gate insulator by carrying out a first directional deposition procedure, and/or a second gate portion of the gate structure is selectively formed extending at least partially along a second vertical surface of the gate insulator by carrying out a second directional deposition procedure.

13. A method of manufacturing a transistor device, the method comprising:

forming a fin extending along a horizontal direction on a substrate;

forming a first source/drain region of a first type of conductivity in the fin;

forming a second source/drain region of a second type of conductivity in the fin, wherein the first type of conductivity differs from the second type of conductivity;

forming a channel region in the fin between the first source/drain region and the second source/drain region;

forming a gate insulator on the channel region;

forming a gate structure on the gate insulator;

forming the sequence of the first source/drain region, the channel region and the second source/drain region to be aligned along the horizontal direction.

14. The method according to claim 13, wherein the transistor device is manufactured based on a silicon-on-insulator substrate.

15. The method according to claim 13, wherein the first source/drain region is formed by doping a corresponding portion of the fin with a dopant of the first type of conductivity while the second source/drain region is covered by a first mask layer, and/or the second source/drain region is formed by doping a corresponding portion of the fin with a dopant of the second type of conductivity while the first source/drain region is covered by a second mask layer.