PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL

• US 20100025771A1
• Filed: 05/28/2009
• Published: 02/04/2010
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hannon, Belinda, Hoentschel, Jan, Papageorgiou, Vassilios
• Granted Patent: US 8,154,084 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Claims

1. A method of forming a strained semiconductor material in a first transistor of a first conductivity type and a second transistor of a second conductivity type, the method comprising:

forming a stack of layers above a first gate electrode structure of said first transistor and a second gate electrode structure of said second transistor, said first and second gate electrode structures comprising a respective cap layer, said stack of layers comprising a spacer layer and an etch stop layer formed above said spacer layer;

forming a mask above said second transistor and above said etch stop layer;

forming a first spacer element at said first gate electrode structure from said spacer layer;

forming first cavities in drain and source areas of said first transistor using said first spacer element as a mask;

forming a first strained semiconductor material in said first cavities;

forming second cavities in drain and source areas of said second transistor using a second spacer element formed from said spacer layer as a mask; and

forming a second strained semiconductor material in said second cavities, said first and second strained semiconductor materials having a different material composition.

2. The method of claim 1, further comprising introducing one or more first implantation species into exposed surface portions of said first cavities.

3. The method of claim 2, wherein said one or more first implantation species comprises a non-doping species for modifying a diffusion behavior of a dopant species of drain and source regions of said first transistor.

4. The method of claim 2, wherein said one or more first implantation species comprises a dopant species for forming drain and source regions of said first transistor.

5. The method of claim 1, further comprising introducing one or more second implantation species into exposed surface portions of said second cavities.

6. The method of claim 5, wherein said one or more second implantation species comprises a non-doping species.

7. The method of claim 5, wherein said one or more second implantation species comprises a dopant species for forming drain and source regions of said second transistor.

8. The method of claim 1, wherein forming said second cavities comprises forming a second mask above said first transistor, removing said etch stop layer from above said second transistor and forming said second spacer element.

9. The method of claim 5, wherein said first strained semiconductor material is formed by a first selective epitaxial growth process and said second strained semiconductor material is formed by a second epitaxial growth process.

10. The method of claim 1, further comprising forming one or more stress-inducing spacer elements on sidewalls of said first and second gate electrode structures after forming said first and second strained semiconductor materials.

11. The method of claim 1, further comprising forming a first strain inducing layer above said first transistor and forming a second strain inducing layer above said second transistor, wherein said first and second strain inducing layers induce a different type of strain in channel regions of said first and second transistors.

12. The method of claim 1, wherein said first strained semiconductor material comprises a silicon/germanium alloy and said second strained semiconductor material comprises a silicon/carbon alloy.

13. A method, comprising:

forming first cavities adjacent to a first gate electrode structure of a first transistor and second cavities adjacent to a second gate electrode structure of a second transistor, said first and second transistors being of different conductivity type;

forming a semiconductor material in said first and second cavities, said semiconductor material having a first type of strain;

creating lattice damage in said semiconductor material selectively in said first transistor to form a substantially relaxed semiconductor material; and

re-crystallizing said substantially relaxed semiconductor material in a strained state, said strained state corresponding to a second type of strain that is opposite to said first type of strain.

14. The method of claim 13, wherein re-crystallizing said substantially relaxed semiconductor material comprises forming a strain-inducing material layer above said first transistor and annealing said substantially relaxed semiconductor material in the presence of said strain-inducing material layer.

15. The method of claim 14, wherein said semiconductor material comprises a silicon/carbon alloy.

16. The method of claim 13, wherein said first and second cavities are formed in a common etch process.

17. The method of claim 13, further comprising forming a first strain-inducing layer above metal silicide regions of said first transistor and forming a second strain-inducing layer on metal silicide regions of said second transistor, wherein said first and second strain-inducing layers generate a different type of strain.

18. A semiconductor device, comprising:

a first transistor comprising a silicon/carbon alloy in drain and source regions, said first transistor comprising a channel region exhibiting a first strain component along a channel length direction; and

a second transistor comprising a silicon/carbon alloy in drain and source regions, said second transistor comprising a channel region exhibiting a second strain component along a channel length direction, said first and second strain components being of opposite type.

19. The semiconductor device of claim 18, further comprising a buried insulating layer formed between a carrier material and a semiconductor material accommodating said drain and source regions of said first and second transistors.

20. The semiconductor device of claim 18, wherein said first transistor is an N-channel transistor and said second transistor is a P-channel transistor and wherein said first strain component is a tensile strain and second strain component is a compressive strain.