METAL ADHESION BY INDUCED SURFACE ROUGHNESS

• US 20100025825A1
• Filed: 08/04/2008
• Published: 02/04/2010
• Est. Priority Date: 08/04/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Ping-Chuan, Shih, Da-Yuan, Lindgren, Peter James, DeGraw, Danielle L.
• Granted Patent: US 8,039,314 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01044 Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.

Claims

1. A method of preventing a layer of material from delaminating from a semiconductor surfaces, comprising:

providing a layer of semiconductor material having opposing surfaces with at least one through via structure extending to at least one of said opposing surfaces;

providing a roughened surface region on said at least one of said opposing surfaces beyond said at least one through via structure to promote adhesion of said layer of material to said at least one of said opposing surfaces; and

forming said layer of material on said at least one of said opposing surfaces.

2. The method of claim 1 wherein said layer of material is a layer of metal and said at least one through via structure and vicinity thereof within said roughened surface region is polished.

3. The method of claim 2 wherein said layer of semiconductor material is a semiconductor wafer having an array of chips each having said at least one via structure extending to said at least one surface and said step of providing a roughened surface region is carried out along chip dicing lines of said wafer beyond said via structures.

4. The method of claim 3 wherein said at least one of said opposing surfaces is polished and said step of providing a roughened surface region is carried out by forming masks over at least said at least one through via structure and vicinity thereof leaving said chip dicing lines exposed and exposing said chip dicing lines to a roughening agent.

5. The method of claim 4 wherein the said at least one of said opposing surfaces is roughened throughout and said at least one through via structure and vicinity thereof is polished by forming masks over said roughened surface region along said chip dicing lines leaving said at least one through via structure and vicinity exposed and exposing said roughened surface of said at least one through via structure and vicinity thereof to a polishing agent.

6. The method of claim 5 wherein said step of exposing said chip dicing lines to a roughening agent includes exposing said chip dicing lines to reactive ion etching.

7. The method of claim 6 wherein said reactive ion etching is followed by wet etching.

8. The method of claim 7 wherein said at least one of said opposing surfaces is polished by chemical-mechanical polishing.

9. The method of claim 3 wherein said layer of metal is formed with gaps in said metal between said chips along said chip dicing lines of said wafer.

10. The method of claim 9 wherein said semiconductor wafer is diced along said chip dicing lines.

11. A method of improving metal adhesion in chip fabrication, comprising:

providing a semiconductor wafer with an array of chip regions each having integrated circuits formed at one surface and at least one through via extending from said one surface to the other surface thereof;

polishing the said other surface of said wafer to a smooth surface;

forming a mask pattern on the said smooth surface of said other surface to cover said at least one through via of each of said chip regions of said array of chip regions leaving dicing lines between each of said chip regions exposed;

exposing said dicing lines of said smooth surface of said other surface to a roughening process to roughen said smooth surface along said dicing lines between each of said chip regions while allowing said mask pattern to prevent roughening of said at least one through via of each of said chip regions of said array of chip regions;

removing said mask pattern; and

forming a layer of metal on said other surface.

12. The method of claim 11 wherein said polishing of said other surface includes chemical-mechanical polishing.

13. The method of claim 11 wherein said roughening process includes exposing said dicing lines of said smooth surface of said other surface to reactive ion etching in plasma using C4F8, Co and Ar.

14. The method of claim 13 wherein said reactive ion etching step is followed by wet etching.

15. The method of claim 14 wherein said wafer is diced along said dicing lines.

16. A method of improving chip edge adhesion in thru-silicon-via structures, comprising:

providing a silicon wafer having an array of chip regions each having integrated circuits formed at one surface and at least one thru-silicon-via structure extending from said one surface to a smooth surface of the other surface thereof with said at least one thru-silicon-via structure at least partially filled with a conductive material extending to the said smooth surface of said other surface thereof of said silicon wafer;

forming a mask pattern on the said smooth surface of said other surface to cover said at least one thru-silicon-via of each of said chip regions of said array of chip regions leaving dicing lines between each of said chip regions exposed;

exposing the said smooth surface of said other surface to a roughening process to roughen said smooth surface along said dicing lines between each of said chip regions;

removing said mask pattern;

forming a layer of metal on said other surface; and

removing metal from said layer of metal along said dicing lines between each of said chip regions.

17. The method of claim 16 wherein said roughening process includes exposing said smooth surface of said other surface to reactive ion etching in plasma using C4F8, Co and Ar and then follow by wet etching.

18. The method of claim 17 wherein said wafer is diced along said dicing lines.

19. A wafer structure comprising:

an array of chip regions each having integrated circuits formed at one surface and at least one through via extending from said one surface to the other surface thereof, said other surface being roughened along the dicing lines between each of said chip regions of said array of chip regions and polished at said at least one through via of each of said chip regions; and

a layer of material formed on said other surface.

20. The wafer structure of claim 19 wherein said layer of material is a masking layer.

21. The wafer structure of claim 19 wherein said layer of material is a layer of metal.

22. The wafer structure of claim 21 wherein the said at least one through via extending from the said one surface to said other surface is at least partially filled with a conductive material extending to said other surface as polished.

23. The wafer structure of claim 22 wherein metallurgy formed at said one surface of each of said array of chip regions is connected to said layer of metal by said through via.

24. The structure of claim 23 wherein said layer of metal is patterned to leave gaps in the metal between the said chip regions of said array of chip regions along said dicing lines.

25. The wafer structure of claim 23 diced into chips.