Hybrid-Level Three-Dimensional Mask-Programmable Read-Only Memory

• US 20100025861A1
• Filed: 06/02/2009
• Published: 02/04/2010
• Est. Priority Date: 12/01/2006
• Status: Abandoned Application

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: ZHANG, Guobiao
• Application Number:
  US12/476,263
• Publication Number:
  US 20100025861A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM) includes a plurality of memory sets. Within each memory set, a plurality of vertically stacked memory levels are interleaved and all adjacent memory levels share address-selection lines; between adjacent memory sets, memory levels are separated by an inter-level dielectric and do not share any address-selection lines.

Claims

1. A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM), comprising:

a substrate including transistors;

a first mask-programmable read-only memory level above said substrate and coupled to said substrate;

a second mask-programmable read-only memory level above said first memory level and coupled to said substrate, said first and second memory levels sharing at least one address-selection line;

an inter-level dielectric above said second memory level;

a third mask-programmable read-only memory level above said inter-level dielectric and coupled to said substrate;

a fourth mask-programmable read-only memory level above said third memory level and coupled to said substrate, said third and fourth memory levels sharing at least one address-selection line.

2. The HL-3DMPROM according to claim 1, wherein the total number of memory levels in said HL-3DMPROM is no less than 4.

3. The HL-3DMPROM according to claim 1, wherein at least one of said first, second, third and fourth memory levels comprises passive devices.

4. The HL-3DMPROM according to claim 3, wherein said passive devices comprise diodes.

5. The HL-3DMPROM according to claim 4, wherein said diodes are junction diodes.

6. The HL-3DMPROM according to claim 4, wherein said diodes are Schottky diodes.

7. The HL-3DMPROM according to claim 1, wherein at least one of said first, second, third and fourth memory levels comprises active devices.

8. A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM), comprising:

a substrate including transistors;

a plurality of vertically stacked mask-programmable read-only memory levels above said substrate and coupled to said substrate;

wherein each of said memory levels shares at least one address-selection line with at least one adjacent memory level, and at least a selected one of said memory levels does not share any address-selection lines with one adjacent memory level.

9. The HL-3DMPROM according to claim 8, wherein said selected memory level is separated from one adjacent memory level by an inter-level dielectric.

10. The HL-3DMPROM according to claim 8, wherein the total number of memory levels in said HL-3DMPROM is no less than 4.

11. The HL-3DMPROM according to claim 8, wherein said memory levels comprise passive devices.

12. The HL-3DMPROM according to claim 11, wherein said passive devices comprise diodes.

13. The HL-3DMPROM according to claim 8, wherein said memory levels comprises active devices.

14. A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM), comprising:

a substrate including transistors;

a first 3D-MPROM set above said substrate and coupled to said substrate;

an inter-level dielectric above said first 3D-MPROM set;

a second 3D-MPROM set above said inter-level dielectric and coupled to said substrate;

wherein each of said first and second 3D-MPROM sets comprises a plurality of vertically stacked and interleaved mask-programmable read-only memory levels, and all adjacent memory levels in each of said first and second 3D-MPROM sets share address-selection lines.

15. The HL-3DMPROM according to claim 14, wherein the total number of memory levels in said HL-3DMPROM is no less than 4.

16. The HL-3DMPROM according to claim 14, wherein said memory levels comprise passive devices.

17. The HL-3DMPROM according to claim 16, wherein said passive devices comprise diodes.

18. The HL-3DMPROM according to claim 14, wherein said memory levels comprises active devices.

19. The HL-3DMPROM according to claim 14, wherein said first and second 3D-MPROM sets comprise same number of memory levels.

20. The HL-3DMPROM according to claim 14, wherein said first and second 3D-MPROM sets comprise different number of memory levels.