ALL DIGITAL FREQUENCY-LOCKED LOOP CIRCUIT METHOD FOR CLOCK GENERATION IN MULTICORE MICROPROCESSOR SYSTEMS

• US 20100026352A1
• Filed: 07/30/2008
• Published: 02/04/2010
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Stigliani, Daniel J. JR., Jacobowitz, Lawrence
• Granted Patent: US 7,764,132 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.

Claims

1. A digital frequency locked-loop (DFLL) circuit residing on a local core of a multi-core microprocessor system for generating a local core clock with a frequency value for driving the local core, comprising:

a micro-controller configured to receive a plurality of digital data for characterizing the local core;

a digitally-controlled ring oscillator configured to generate the local core clock for the local core, the digitally-controlled ring oscillator having a delay chain disposed between an output of the digitally-controlled ring oscillator and a feedback input of the digitally-controlled ring oscillator, the delay chain having a plurality of delay taps each receiving the local core clock from the output through the feedback input of the digitally-controlled ring oscillator for enabling single or multi-step quantum changes in the frequency value of the local core clock; and

a counter device configured to continually validate the frequency value of the local core clock by generating a digital signal representative of the frequency value to the micro-controller, the micro-controller compares the frequency value of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device, and the micro-controller selects one of the plurality of delay taps based on the comparison to adjust the frequency value of the local core clock towards alignment with the desired clock frequency.

2. The DFLL circuit as in claim 1, wherein the plurality of digital data includes a transfer function being programmable to the digitally-controlled ring oscillator and stored in the micro-controller, the transfer function calibrates a plurality of time delays correspondingly associated with the plurality of delay taps, the plurality of time delays provide a range of clock frequencies among the plurality delay taps.

3. The DFLL circuit as in claim 2, wherein the transfer function enables the powering down of the local core and the management of workload among each local core within the multi-core microprocessor system.

4. The DFLL circuit as in claim 1, wherein the plurality of digital data includes the desired clock frequency.

5. The DFLL circuit as in claim 1, wherein the micro-controller generates a correction signal based on the comparison, the correction signal being used to select one of the plurality of delay taps.

6. The DFLL circuit as in claim 5, wherein the digitally-controlled ring oscillator includes a digital selector, the digital selector selects one of the plurality of delay taps based on the correction signal and the local core clock received by each of the plurality of delay taps.

7. The DFLL circuit as in claim 1, wherein the counter device includes a low-order binary counter and a high-order binary counter each having operations being controlled by the micro-controller.

8. The DFLL circuit as in claim 1, wherein the micro-controller is configured to receive a reference clock frequency reference for operably clocking the plurality of digital data and the counter device.

9. The DFLL circuit as in claim 1, wherein the plurality of digital data enables direct digital frequency tuning of the frequency value of the local core clock.

10. The DFLL circuit as in claim 1, wherein the micro-controller, the digitally controlled ring oscillator, and the counter device are in signal communication with one another forming a digital feedback network.

11. A method for tuning the frequency of a local core clock configured to drive a local core in a multi-core microprocessor system, the method comprising:

disposing a digital frequency locked-loop (DFLL) circuit on the local core;

generating a digital signal representative of the frequency of the local core clock to a micro-controller of the DFLL circuit when the frequency of the local core clock is validated by a counter device of the DFLL circuit;

comparing the frequency of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device; and

selecting one of a plurality of delay taps of a delay chain in a digitally controlled ring oscillator of the DFLL circuit based on the comparison to adjust the frequency of the local core clock towards alignment with the desired clock frequency, the plurality of delay taps each receive the local core clock from an output end of the digitally controlled ring oscillator, the plurality of delay taps enable single or multi-step quantum changes in the frequency of the local core clock.

12. The method as in claim 11, wherein the digitally controlled ring oscillator is configured to generate the local core clock for the local core.

13. The method as in claim 11, wherein the micro-controller is configured to receive a plurality of digital data for characterizing the local core.

14. The method as in claim 13, wherein the plurality of digital data includes a transfer function being programmable to the digitally-controlled ring oscillator and stored in the micro-controller, the transfer function calibrates a plurality of time delays correspondingly associated with the plurality of delay taps, the plurality of time delays provide a range of clock frequencies among the plurality delay taps.

15. The method as in claim 14, wherein the transfer function enables the powering down of the local core and the management of workload among each local core within the multi-core microprocessor system.

16. The method as in claim 13, wherein the plurality of digital data includes the desired clock frequency.

17. The method as in claim 11, wherein the micro-controller generates a correction signal based on the comparison, the correction signal being used to select one of the plurality of delay taps.

18. The method as in claim 17, wherein the digitally-controlled ring oscillator includes a digital selector, the digital selector selects one of the plurality of delay taps based on the correction signal and the local core clock received by each of the plurality of delay taps.

19. The method as in claim 11, wherein the counter device includes a low-order binary counter and a high-order binary counter each having operations being controlled by the micro-controller.

20. The method as in claim 11, wherein the plurality of digital data enables direct digital frequency tuning of the frequency of the local core clock.