PROTECTION AGAINST FAULT INJECTIONS OF AN ELECTRONIC CIRCUIT WITH FLIP-FLOPS

• US 20100026358A1
• Filed: 07/28/2009
• Published: 02/04/2010
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Roquelaure, Philippe, Bancel, Frederic
• Granted Patent: US 8,466,727 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: H03K 3/0372 of the master-slave type

Abstract

A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance.

Claims

1. A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type comprising two bistable circuits in series, wherein:

the bistable circuits are triggered by two first signals different from each other; and

the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance.

2. The method of claim 1, wherein the second signals are sampled on edges of the first signals.

3. The method of claim 1, wherein the first signals are generated so that the bistable circuits are controlled cyclically in four successive periods in which:

both circuits are latched;

only a first circuit is latched;

both circuits are latched; and

only a second circuit is latched.

4. The method of claim 3, wherein the periods where both circuits are latched provide, on the second signals, states indicative of a possible disturbance.

5. The method of claim 1, wherein a constant level of one of the first signals deactivates the detection.

6. A master-slave synchronous flip-flop comprising two bistable circuits in series, and comprising:

two terminals of application of triggering signals different from each other; and

a first logic circuit for detecting a disturbance of the state of the flip-flop by comparing the states at the flip-flop input, between the two bistable circuits, and at the flip-flop output.

7. The flip-flop of claim 6, wherein a second logic circuit is interposed between the two terminals of application of the triggering signals and respective triggering terminals of the bistable circuits.

8. The flip-flop of claim 6, wherein the first logic circuit comprises two comparators respectively of the data input with the intermediary value, and of this intermediary value with the output.

9. The flip-flop of claim 7, wherein the second logic circuit comprises:

an OR-type gate having its respective inputs connected to the terminals of application of the triggering signals and having an output connected to the triggering terminal of the first bistable circuit; and

an inverter between one of the terminals of application of the triggering signals and the triggering terminal of the second bistable circuit.

10. An electronic circuit comprising at least one logic combination block and at least one set of master-slave synchronous flip-flops, wherein at least one of the flip-flops is in accordance with claim 6.

11. The electronic circuit of claim 10, wherein not all flip-flops are controlled at the same time in comparison mode.