METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY

• US 20100026378A1
• Filed: 02/03/2009
• Published: 02/04/2010
• Est. Priority Date: 05/07/2008
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Schneider, Clayton E. JR., Subbarao, Prasad, Rao, Vishwas M., Sheets, Gregory W., Parker, James C.
• Granted Patent: US 8,806,408 B2
• Time in Patent Office: Days
• US Class Current: 327/538
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.

Claims

1. A method of designing an integrated circuit, comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, whether said integrated circuit is to employ static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to implement a layout from said functional integrated circuit design that meets said performance objectives; and

performing a timing signoff of said layout at said optimization target voltage.

2. The method as recited in claim 1 wherein said using comprises:

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives; and

implementing a layout of said integrated circuit from said netlist.

3. The method as recited in claim 1 wherein said performance objectives include one selected from the group consisting of:

a target power consumption,

a target area, and

a target speed.

4. The method as recited in claim 1 wherein said using comprises:

synthesizing a clock tree for said integrated circuit; and

determining a routing at said optimization target voltage.

5. The method as recited in claim 1 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

6. The method as recited in claim 1 wherein said adaptive voltage scaling is capable of being carried out without software control.

7. The method as recited in claim 1 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

9. The method as recited in claim 1 further comprising determining a target area for said functional integrated circuit design.

10. The method as recited in claim 1 further comprising determining a target power consumption for said functional integrated circuit design.

11. The method as recited in claim 1 further comprising determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling.

12. The method as recited in claim 1 wherein said attempting comprises attempting to increase said performance/power ratio by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist.

13. The method as recited in claim 1 wherein said attempting comprises attempting to increase said performance/power ratio by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist.

14. The method as recited in claim 1 wherein said attempting is carried out only with respect to true noncritical paths in said netlist.

22. An integrated circuit designed by the method as recited in claim 1.

8. A method of designing an integrated circuit, comprising:

generating a functional integrated circuit design;

determining a target clock rate for said functional integrated circuit design;

synthesizing a netlist from said functional integrated circuit design that meets said target clock rate;

determining a performance/power ratio from said netlist;

attempting to increase said performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in said netlist; and

implementing a layout of said integrated circuit from said netlist.

23. An integrated circuit designed by the method as recited in claim 8.

15. A method of designing an integrated circuit, comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit, said performance objectives including one selected from the group consisting of;

a target power consumption,

a target area, and

a target speed;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, whether said integrated circuit is to employ static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives and a clock tree for said integrated circuit;

determining a routing at said optimization target voltage;

implementing a layout of said integrated circuit from said netlist; and

performing a timing signoff of said layout at said optimization target voltage.

16. The method as recited in claim 15 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

17. The method as recited in claim 15 wherein said adaptive voltage scaling is capable of being carried out without software control.

18. The method as recited in claim 15 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

24. An integrated circuit designed by the method as recited in claim 15.

19. A method of designing an integrated circuit, comprising:

generating a functional integrated circuit design;

determining a target clock rate for said functional integrated circuit design;

determining a target area for said functional integrated circuit design;

determining a target power consumption for said functional integrated circuit design;

determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling;

synthesizing a netlist from said functional integrated circuit design that meets said target clock rate;

determining a performance/power ratio from said netlist;

attempting to increase said performance/power ratio by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist; and

implementing a layout of said integrated circuit from said netlist.

20. The method as recited in claim 19 wherein said attempting comprises attempting to increase said performance/power ratio by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist.

21. The method as recited in claim 19 wherein said attempting is carried out only with respect to true noncritical paths in said netlist.

25. An integrated circuit designed by the method as recited in claim 19.

26. An integrated circuit, comprising:

functional circuitry located in at least one drive voltage domain;

at least one PVT monitor and at least one thermal monitor located in said at least one domain;

a voltage management unit configured to receive output signals from said at least one PVT monitor and said at least one thermal monitor and determine at least one drive voltage for said at least one domain based thereon; and

a regulator coupled to said voltage management unit and configured to provide said at least one drive voltage.

27. The integrated circuit as recited in claim 26 further comprising at least one critical path detector located in said at least one domain, said voltage management unit further configured to receive output signals from said at least one critical path monitor and determine said at least one drive voltage based thereon.

28. The integrated circuit as recited in claim 26 wherein said regulator includes an integrated regulator.

29. The integrated circuit as recited in claim 26 wherein said regulator includes an integrated power controller.

30. The integrated circuit as recited in claim 26 wherein said regulator includes a commercial regulator interface.

31. The integrated circuit as recited in claim 26 wherein said regulator includes a system-specific interface.

32. The integrated circuit as recited in claim 26 further comprising a host processor coupled to said voltage management unit.