SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE

• US 20100026619A1
• Filed: 10/06/2006
• Published: 02/04/2010
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: UMEZAKI, Atsushi
• Granted Patent: US 9,153,341 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

Claims

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor,

wherein one of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain of the first transistor is connected to a gate electrode of the second transistor and the other of a source and a drain of the third transistor, and a gate electrode of the first transistor is connected to a fifth wire;

wherein one of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain of the second transistor is connected to a sixth wire;

wherein one of the source and the drain of the third transistor is connected to a second wire, the other of the source and the drain of the third transistor is connected to the gate electrode of the second transistor, and a gate electrode of the third transistor is connected to a fourth wire;

wherein one of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain of the fourth transistor is connected to the sixth wire, and a gate electrode of the fourth transistor is connected to the fourth wire;

wherein the first wire is connected to a power source line; and

wherein the second wire is connected to an input terminal.

3. The semiconductor device according to claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-channel transistors.

5. The semiconductor device according to claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are p-channel transistors.

7. The semiconductor device according to claim 1, wherein semiconductor layers of the first transistor, the second transistor, the third transistor, and the fourth transistor are formed of amorphous silicon.

17. The semiconductor device according to claim 1, wherein a capacitor is provided between the gate electrode of the second transistor and the other of the source and the drain of the second transistor.

21. A shift register comprising the semiconductor device according to claim 1.

25. A display device comprising the shift register according to claim 21 and a plurality of pixels arranged in matrix, wherein the plurality of pixels are driven by the shift register.

29. A display device comprising:

a first shift register according to claim 21, a second shift register according to claim 21, and a plurality of pixels arranged in matrix,

wherein the plurality of pixels are scanned by the first shift register and the second shift register; and

wherein the first shift register scans the plurality of pixels and the second shift register selects the plurality of pixels at the same timing.

33. An electronic device provided with the display device according to claim 25.

37. An electronic device provided with the display device according to claim 29.

2. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor,

wherein one of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain of the first transistor is connected to a gate electrode of the second transistor and the other of a source and a drain of the third transistor, and a gate electrode of the first transistor is connected to the fifth wire;

wherein one of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain of the second transistor is connected to a sixth wire;

one of the source and the drain of the third transistor is connected to a second wire, the other of the source and the drain of the third transistor is connected to the gate electrode of the second transistor, and a gate electrode of the third transistor is connected to a fourth wire;

wherein one of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain of the fourth transistor is connected to the sixth wire, and a gate electrode of the fourth transistor is connected to the fourth wire; and

wherein a clock signal is input to the fourth wire.

4. The semiconductor device according to claim 2, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-channel transistors.

6. The semiconductor device according to claim 2, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are p-channel transistors.

8. The semiconductor device according to claim 2, wherein semiconductor layers of the first transistor, the second transistor, the third transistor, and the fourth transistor are formed of amorphous silicon.

18. The semiconductor device according to claim 2, wherein a capacitor is provided between the gate electrode of the second transistor and the other of the source and the drain of the second transistor.

22. A shift register comprising the semiconductor device according to claim 2.

26. A display device comprising the shift register according to claim 22 and a plurality of pixels arranged in matrix, wherein the plurality of pixels are driven by the shift register.

30. A display device comprising:

a first shift register according to claim 22, a second shift register according to claim 22, and a plurality of pixels arranged in matrix,

wherein the plurality of pixels are scanned by the first shift register and the second shift register; and

wherein the first shift register scans the plurality of pixels and the second shift register selects the plurality of pixels at the same timing.

34. An electronic device provided with the display device according to claim 26.

38. An electronic device provided with the display device according to claim 30.

41. The semiconductor device according to claim 2, wherein the first wire is connected to the fifth wire.

9. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein one of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain of the first transistor is connected to a gate electrode of the second transistor and the other of a source and a drain of the third transistor, and a gate electrode of the first transistor is connected to a fifth wire;

wherein one of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain of the second transistor is connected to a sixth wire;

wherein one of the source and the drain of the third transistor is connected to a second wire, the other of the source and the drain of the third transistor is connected to the gate electrode of the second transistor, and a gate electrode of the third transistor is connected to a fourth wire;

wherein one of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain of the fourth transistor is connected to the sixth wire, and a gate electrode of the fourth transistor is connected to the fourth wire;

wherein one of a source and a drain of the fifth transistor is connected to the second wire, the other of the source and the drain of the fifth transistor is connected to the sixth wire, and a gate electrode of the fifth transistor is connected to a seventh wire;

wherein the first wire is connected to a power source line; and

wherein the second wire is connected to an input terminal.

11. The semiconductor device according to claim 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-channel transistors.

13. The semiconductor device according to claim 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are p-channel transistors.

15. The semiconductor device according to claim 9, wherein semiconductor layers of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are formed of amorphous silicon.

19. The semiconductor device according to claim 9, wherein a capacitor is provided between the gate electrode of the second transistor and the other of the source and the drain of the second transistor.

23. A shift register comprising the semiconductor device according to claim 9.

27. A display device comprising the shift register according to claim 23 and a plurality of pixels arranged in matrix, wherein the plurality of pixels are driven by the shift register.

31. A display device comprising:

a first shift register according to claim 23, a second shift register according to claim 23, and a plurality of pixels arranged in matrix,

wherein the plurality of pixels are scanned by the first shift register and the second shift register; and

wherein the first shift register scans the plurality of pixels and the second shift register selects the plurality of pixels at the same timing.

35. An electronic device provided with the display device according to claim 27.

39. An electronic device provided with the display device according to claim 31.

10. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein one of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain of the first transistor is connected to a gate electrode of the second transistor and the other of a source and a drain of the third transistor, and a gate electrode of the first transistor is connected to the fifth wire;

wherein one of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain of the second transistor is connected to a sixth wire;

wherein one of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain of the third transistor is connected to the gate electrode of the second transistor, and a gate electrode of the third transistor is connected to a fourth wire;

wherein one of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain of the fourth transistor is connected to the sixth wire, and a gate electrode of the fourth transistor is connected to the fourth wire;

wherein one of a source and a drain of the fifth transistor is connected to the second wire, the other of the source and the drain of the fifth transistor is connected to the sixth wire, and a gate electrode of the fifth transistor is connected to a seventh wire; and

wherein a clock signal is input to the fourth wire.

12. The semiconductor device according to claim 10, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-channel transistors.

14. The semiconductor device according to claim 10, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are p-channel transistors.

16. The semiconductor device according to claim 10, wherein semiconductor layers of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are formed of amorphous silicon.

20. The semiconductor device according to claim 10, wherein a capacitor is provided between the gate electrode of the second transistor and the other of the source and the drain of the second transistor.

24. A shift register comprising the semiconductor device according to claim 10.

28. A display device comprising the shift register according to claim 24 and a plurality of pixels arranged in matrix, wherein the plurality of pixels are driven by the shift register.

32. A display device comprising:

a first shift register according to claim 24, a second shift register according to claim 24, and a plurality of pixels arranged in matrix,

wherein the plurality of pixels are scanned by the first shift register and the second shift register; and

wherein the first shift register scans the plurality of pixels and the second shift register selects the plurality of pixels at the same timing.

36. An electronic device provided with the display device according to claim 28.

40. An electronic device provided with the display device according to claim 32.

42. The semiconductor device according to claim 10, wherein the first wire is connected to the fifth wire.