SOLID-STATE IMAGE PICK-UP DEVICE, DATA TRANSMISSION METHOD, AND IMAGE PICKUP APPARATUS

• US 20100026814A1
• Filed: 06/26/2007
• Published: 02/04/2010
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Shimoda, Tetsuya
• Granted Patent: US 8,169,499 B2
• Time in Patent Office: Days
• US Class Current: 348/207.100
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A video camera (100) for transmitting image data from an image pickup device to an image processing device with reduced electric power includes a C-MOS image sensor (110) that reads captured image data on the basis of a reference clock CLK0, a frequency multiplying circuit (121) that generates a high-speed clock CLK1, a rearranging circuit (122) that transposes the captured image data into bit data sequences, a data output section (120) that causes each data transmitter (124) to sequentially transmit a corresponding bit data sequence to the outside on the basis of the high-speed clock CLK1, and a system controller (400) that drives data transmitters (124), the number of which is proportional to a transmission speed.

Claims

1. A solid-state image pickup device characterized by comprising:

a solid-state image pickup element that reads, on the basis of a first clock, captured image data items from unit pixels 21 that are arranged two-dimensionally;

a second clock generation unit that generates a second clock having an operating frequency higher than that of the first clock;

an arrangement processing unit that rearranges the captured image data items read from the solid-state image pickup element into bit data sequences;

a data transmission unit that includes a plurality of differential amplifiers for transmitting the bit data sequences rearranged by the arrangement processing unit through a plurality of differential transmission channels to the outside, the differential amplifiers transmitting the bit data sequences to the outside on the basis of the second clock; and

a control unit that drives differential amplifiers, the number of which is proportional to a transmission speed at which the captured image data items are transmitted to the outside.

2. The solid-state image pickup device according to claim 1, characterized in that the second clock generation unit generates the second clock, which is obtained by multiplication of the operating frequency of the first clock.

3. The solid-state image pickup device according to claim 1, characterized in that the solid-state image pickup element reads pixel data items in a plurality of columns per unit time on the basis of the first clock, and the arrangement processing unit rearranges the pixel data items in the plurality of columns into the bit data sequences.

4. A data transmission method for outputting, through a plurality of differential transmission channels to the outside, captured image data items read from a solid-state image pickup element in which unit pixels are arranged two-dimensionally, the data transmission method being characterized by comprising:

rearranging the captured image data items read from the solid-state image pickup element into a predetermined number of bit data sequences;

generating a second clock having an operating frequency higher than that of the first clock;

driving differential amplifiers, the number of which is proportional to a transmission speed at which the captured image data items are transmitted to the outside; and

transmitting, for the individual driven differential amplifiers, each of the rearranged bit data sequences to the outside on the basis of the second clock.

5. An image pickup apparatus comprising an image pickup processing section that reads, on the basis of a first clock, captured image data items from a solid-state image pickup element in which unit pixels are arranged two-dimensionally, and an image processing section that performs predetermined data processing on the captured image data items read from the image pickup processing section, the image pickup apparatus being characterized in that:

the image pickup processing section includes

a second clock generation unit that generates a second clock having an operating frequency higher than that of the first clock,

an arrangement processing unit that rearranges the captured image data items read from the solid-state image pickup element into a predetermined number of bit data sequences,

a data transmission unit that includes a plurality of differential amplifiers for transmitting the bit data sequences rearranged by the arrangement processing unit through a plurality of differential transmission channels to the outside, the differential amplifiers transmitting the bit data sequences to the outside on the basis of the second clock, and

a control unit that drives differential amplifiers, the number of which is proportional to a transmission speed at which the captured image data items are transmitted to the image processing section.