IMAGE ACQUISITION SYSTEM

• US 20100026844A1
• Filed: 07/31/2009
• Published: 02/04/2010
• Est. Priority Date: 06/28/1996
• Status: Active Grant

• Current Assignee: Metrovideo Incorporated
• Original Assignee: Metrovideo Incorporated
• Inventors: Hopkins, T. Eric
• Granted Patent: US 9,491,346 B2
• Time in Patent Office: Days
• US Class Current: 348/231.200
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06T 1/0007 Image acquisition
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

An image acquisition system for machine vision systems decouples image acquisition from the transmission of the image to a host processor by using a programmable imager controller to selectively disable and enable the transmission of data to the host and by using a system of buffers to temporarily store image data pending allocation of memory. This enables the image acquisition system to acquire images asynchronously and to change the exposure parameters on a frame-by-frame basis without the latency associated with the allocation of memory for storage of the acquired image. The system architecture of the invention further permits interruption and resumption of image acquisition with minimal likelihood of missing data. Data throughput is further enhanced by transmitting to the host only that data corresponding to the region of interest within the image and discarding the data from outside of the region of interest at the camera stage.

Claims

1. A system for transmitting images to a machine vision system having a host processor that allocates memory for storage of said images acquired by said system, said system comprising:

image acquisition means responsive to at least one trigger signal asserted by external components for acquiring one or more of said images in response to at least one of said trigger signals,

host memory means for storing data representative of a portion of one or more of said images, and

image transfer means for controlling transfer of one or more of said images from said image acquisition means to said host memory means,

said transfer means having buffer memory associated with one or more data path levels for transferring a plurality of said images pending at least allocation of memory space in said host memory means by the host processor for portions of said images,

wherein said image acquisition means operates substantially independently of the allocation of memory by the host processor to acquire the plurality of images at any time relative to allocation of the memory space in said host memory means.

2. A system according to claim 1 wherein said buffer memory comprises a data FIFO register, said data FIFO register being coupled to receive data representative of said images from said image acquisition means and to release data representative of said images to the host processor in response to a release signal.

3. A system according to claim 1, wherein said buffer memory comprises a plurality of registers, said plurality of registers being coupled to receive data representative of said images from said image acquisition means in response to said one or more trigger signals and to release data representative of said images to the host processor in response to a release signal.

4. A system according to claim 1, wherein said image acquisition means comprises

photo-sensitive means for acquiring said images in response to said trigger signals containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said trigger signals and for programmably altering during acquisition of said images said selected image acquisition parameters.

5. A system according to claim 4, wherein said photo-sensitive means includes a solid state imaging array and said programmable control means includes a programmable imager controller.

6. A system according to claim 4, wherein said programmable control means comprises:

a controller adapted to be programmed with said selected image acquisition parameters and for generating said one or more trigger signals in response to a loading signal, and

parameter loading means coupled to said controller for generating said loading signal and for receiving said image acquisition parameters.

7. A system according to claim 4, wherein said programmable control means includes a programmable image controller circuit, said controller circuit being adapted to be programmed with said image acquisition parameters.

8. A system according to claim 7, wherein said programmable image controller circuit includes means for receiving said image acquisition parameters in less than or equal to about 2 μ

s.

9. A system according to claim 7, wherein said programmable image controller circuit includes means for reprogramming said circuit on the fly, in essentially real time.

10. A system according to claim 7, wherein said programmable image controller circuit operates at a driving frequency, said programmable image controller circuit comprising means for automatically changing said driving frequency during acquisition of said images.

11. A system according to claim 6, further comprising

actuation means for generating an output actuation signal in response to an input command signal, said parameter loading means generating said loading signal in response to said actuation signal, and

parameter memory means, in communication with said parameter loading means, for receiving said image acquisition parameters from the host processor.

12. A system according to claim 4, wherein said image acquisition means further includes

actuation means for generating an output actuation signal in response to a command signal,

parameter memory means in communication with said programmable control means for receiving said image acquisition parameters from the host processor, and

a camera loader circuit adapted to receive said selected image acquisition parameters from said parameter memory means and said output actuation signal, for programming said programmable control means with said image acquisition parameters.

13. A system according to claim 4, wherein said buffer memory comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired images, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said one or more vertical registers.

14. A system according to claim 13, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said images, and wherein said means for transferring transfers a portion of said optical energy corresponding to a portion of said region of interest from said vertical registers into said horizontal registers, further comprising

disabling means for disabling transfer of said optical energy from said one or more horizontal registers during said transfer of optical energy from said one or more vertical registers into said one or more horizontal registers,

whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said one or more vertical registers to said one or more horizontal registers without actively removing said stored energy from said one or more horizontal registers.

15. A system according to claim 14, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said images, and wherein said means for transferring transfers a portion of said energy stored in said vertical register corresponding to a portion of said region of interest into said horizontal register, further comprising

enabling means for enabling transfer of said optical energy stored in said horizontal registers therefrom, and

disabling means for disabling transfer of optical energy from said vertical registers into said horizontal registers during said transfer of optical energy out of said horizontal registers.

16. A system according to claim 2, further comprising direct memory address data transfer means for transferring said image data accumulated in said data FIFO register directly to memory allocated in the host computing system, whereby said data transfer substantially reduces the number of times said system interrupts the host processor.

17. A system according to claim 2, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without substantially interrupting the host processor.

18. A system according to claim 2, further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said images when said data FIFO register is at least substantially full, thereby permitting reliable transfer of data corresponding to said images.

19. A system according to claim 18, wherein said images are composed of a plurality of lines, and wherein said interrupt means is capable of interrupting said acquisition of said images between said lines corresponding to said images.

20. A system according to claim 2, further comprising feedback means coupled between said image acquisition means and said data FIFO register for monitoring said status of said data FIFO register and for transferring an interrupt signal to said image acquisition means to interrupt said acquisition of said images, said feedback means including interrupt means coupled to said data FIFO register for generating said interrupt signal when said data FIFO register is at least substantially full, whereby said interrupt means immediately and temporarily interrupts said acquisition of said images.

21. A system according to claim 1, wherein said image acquisition means acquires said images in parallel with and substantially independently of allocation of memory by the host processor.

22. A system according to claim 1, wherein said images acquired by said image acquisition means includes a plurality of pixels, further comprising pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means.

23. A system according to claim 22, wherein said pixel correction means comprises

second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said images, and

multiplier means for multiplying each pixel of said images by said corresponding pixel correction value, thereby forming a corrected pixel.

24. A system according to claim 22, wherein said pixel correction means is separate from the host processor and performs said pixel correction in real time.

25. A system according to claim 4, wherein said images have a region of interest corresponding to a portion of said images, said region of interest having a selected number of pixels, further comprising

pixel evaluation memory means coupled to image acquisition means for storing a value corresponding to said selected number of pixels, and

pre-determined pixel storage means coupled to said image acquisition means for storing a value corresponding to a predetermined number of pixels.

26. A system according to claim 25, further comprising

comparing means for comparing said value stored in said pixel evaluation memory means with said value stored in said pre-determined pixel storage means, and

means for generating a match signal when said values are equal, said programmable control means including means for receiving said match signal and for altering said image acquisition parameters.