PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL

• US 20100027355A1
• Filed: 07/31/2007
• Published: 02/04/2010
• Est. Priority Date: 07/31/2007
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: White, Bruce E., Thean, Voon-Yew, Dao, Thuy B.
• Application Number:
  US11/831,801
• Publication Number:
  US 20100027355A1
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body.

Claims

1. A semiconductor device suitable for use as a storage cell, comprising:

a semiconductor body having a top surface and a bottom surface;

a top gate dielectric overlying the semiconductor body top surface;

an electrically conductive top gate electrode overlying the top gate dielectric;

a bottom gate dielectric underlying the semiconductor body bottom surface;

an electrically conductive bottom gate electrode underlying the bottom gate dielectric; and

a charge trapping layer, comprising a plurality of shallow charge traps, overlying the top or underlying the bottom surface of the semiconductor body.

2. The device of claim 1, wherein the charge trapping layer comprises a material selected from the group consisting of aluminum oxide, silicon nitride, and silicon nanoclusters.

3. The device of claim 1, wherein the charge trapping layer is intermediate between the bottom gate dielectric and the bottom surface of the semiconductor body.

4. The device of claim 1, wherein the semiconductor body is substantially single crystal silicon.

5. The device of claim 1, wherein the top gate dielectric differs from the bottom gate dielectric with respect to at least one characteristic selected from the group of characteristics consisting of effective oxide thickness and material.

6. The device of claim 1, wherein the top gate electrode differs from the bottom gate electrode with respect to at least one characteristic selected from the group of characteristics consisting of thickness, material, conductivity, work function, length, and width.

7. The device of claim 1, further comprising:

source/drain regions laterally displaced on either side of the semiconductor body and aligned to the top gate electrode;

isolation regions adjacent to the source/drain regions;

a buried oxide (BOX) layer underlying the bottom gate electrode; and

a semiconductor substrate underlying the BOX layer;

wherein;

the charge trapping layer comprises a layer of a trapping material selected from the group consisting of aluminum oxide, silicon nitride, and a silicon nanoclusters layer comprising a plurality of silicon nanoclusters;

the charge trapping layer is located in close proximity to the interface between the bottom gate dielectric and the semiconductor body;

the top gate dielectric and bottom gate dielectric include at least one material selected from the group consisting of thermally formed silicon dioxide and a high-K dielectric;

the top gate electrode and bottom gate electrode include at least one material selected from the group consisting of polycrystalline silicon, α

-silicon, α

-germanium, W, Ti, Ta, TiN, TaSiN, and silicide; and

the semiconductor body comprises crystalline silicon.

8. A semiconductor fabrication method comprising:

forming a bottom gate electrode;

forming a bottom gate dielectric overlying the bottom gate electrode;

forming a charge trapping layer, having a density of shallow charge traps exceeding a specified threshold, overlying the bottom gate electrode;

forming a semiconductor body overlying the charge trapping layer;

forming a top gate dielectric overlying the semiconductor body; and

forming a top gate electrode overlying the top gate dielectric.

9. The method of claim 8, wherein forming the bottom gate electrode comprises forming the bottom gate electrode overlying a buried oxide (BOX) layer.

10. The method of claim 8, wherein the bottom gate electrode, the bottom gate dielectric, and the charge trapping layer are formed overlying a semiconductor layer of a donor wafer and wherein the method further includes bonding the donor wafer to a handle wafer.

11. The method of claim 10, further comprising, after said bonding, cleaving the semiconductor layer of the substrate wherein the semiconductor body comprises a portion of the cleaved portion.

12. The method of claim 11, wherein the semiconductor body comprises single crystal silicon.

13. The method of claim 8, wherein forming the charge trapping layer includes forming a layer of a dielectric selected from the group consisting of aluminum oxide and silicon nitride.

14. The method of claim 13, wherein forming the charge trapping layer comprises forming the charge trapping layer by atomic layer deposition.

15. The method of claim 8, wherein forming the charge trapping layer comprises forming a layer of silicon nanoclusters.

16. A method of operating a semiconductor device as a storage cell, comprising:

writing the cell by biasing a top gate electrode overlying a top gate dielectric and a semiconductor body to a first top gate write voltage, biasing a bottom gate electrode underlying a bottom gate dielectric underlying the semiconductor body to a first bottom gate write voltage, biasing a drain electrode laterally positioned adjacent to a transistor channel of the semiconductor body underlying the first gate electrode to a first drain write voltage, and biasing a source terminal laterally positioned adjacent the transistor channel to ground; and

reading the cell by biasing the top gate electrode to a top gate read voltage, biasing the bottom gate electrode to a bottom gate read voltage, biasing the drain electrode to a drain read voltage, and biasing the source terminal laterally positioned adjacent the transistor channel to ground

wherein said writing includes storing charge in a charge trapping layer of the semiconductor device wherein the charge trapping layer is located in close proximity to a surface of the semiconductor body and includes a plurality of charge traps.

17. The method of claim 16 wherein said writing comprises writing a first value and further comprising writing a second value in the storage cell by biasing the top gate electrode to a second top gate write voltage, biasing the bottom gate electrode to a second bottom gate write voltage, biasing the drain electrode to a second drain write voltage, and biasing the source terminal to ground.

18. The method of claim 16 wherein the plurality of charge traps comprise a plurality of shallow hole traps having an activation energy less than approximately 0.3 eV and a density of greater than approximately 1E12 traps/cm².

19. The method of claim 18 wherein said first top gate write voltage is approximately 0.6 V, the first bottom gate write voltage is approximately −

2.0 V, the first drain write voltage is approximately 1.8 V, said second top gate write voltage is approximately 1.0 V, said second bottom gate write voltage is approximately −

0.5 V, and said second drain write voltage is approximately −

1.0 V.

20. The method of claim 19, wherein said top gate read voltage is approximately 0.6 V, said bottom gate read voltage is approximately −

1.5 V, and said drain read voltage is approximately 0.2 V.