EQUALIZING TRANSMITTER AND METHOD OF OPERATION

• US 20100027712A1
• Filed: 01/07/2008
• Published: 02/04/2010
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Poulton, John Wood
• Granted Patent: US 9,148,313 B2
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: H04L 2025/03808 Transmission of equaliser coefficients
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0288 the shape being matched to the transmission line pre-equalisation per se H04L25/03343
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

Claims

1-44. -44. (canceled)

45. A transmitter comprising:

a first driver to generate a first signal representing a digital input signal; and

a second driver having at least one high pass filter to generate a second signal representing a high pass filtered version of the digital input signal, the second signal including a spike corresponding to each transition of the digital input signal, each spike in the second signal having a rapid rise or fall from a zero signal level followed by a gradual decay to the zero signal level, the first and second signals being combined to produce an output signal.

46. The transmitter as claimed in claim 45 wherein the first driver and the second driver are referenced to a same power supply voltage.

47. The transmitter as claimed in claim 46 wherein the ratio of an amplitude of the output signal to an amplitude of the first signal is independent of the power supply voltage.

48. The transmitter as claimed in claim 45 wherein the second signal includes a spike corresponding to a respective transition of the digital input signal.

49. The transmitter as claimed in claim 45 wherein each spike in the second signal has a same sense as the respective transition.

50. The transmitter as claimed in claim 49 wherein the gradual decay follows at least approximately an exponential decay pattern.

51. The transmitter as claimed in claim 45 wherein the second driver is a pulse-mode driver.

52. The transmitter as claimed in claim 45 wherein the at least one high pass filter has at least one of an adjustable frequency cutoff and an adjustable gain.

53. The transmitter as claimed in claim 45 wherein the at least one high pass filter has a frequency cutoff set to be about equal to a bit toggle frequency of the input signal.

54. The transmitter as claimed in claim 45 wherein the at least one high pass filter includes a continuous-time high pass filter comprising a resistor-capacitor network.

55. A monolithic semiconductor chip including one or more transmitters as claimed in claim 45.

56. The transmitter as claimed in claim 45 wherein the transmitter is to be coupled to a channel having a frequency attenuation, and wherein the second driver includes a set of high-pass filters configurable via a set of digital inputs to provide a filter transfer function to offset the frequency attenuation.

57. A system including the transmitter as claimed in claim 56 and a receiver coupled to the transmitter through the channel, the receiver being configured to send a set of coefficients to the transmitter, the coefficient being used by the transmitter to configure the set of high-pass filters.

58. A transmitter comprising:

a driver to generate a first signal representing a digital input signal; and

a passive high-pass network having a high-frequency gain and a DC gain, wherein the passive high-pass network is adapted to receive the digital input signal and to generate a second signal having a spike corresponding to each transition in the digital input signal, the transmitter being configured to combine the first and the second signals to form an output signal.

59. The transmitter as claimed in claim 58 wherein the passive high-pass network has at least one of an adjustable cutoff frequency and an adjustable ratio of the high-frequency gain to the DC gain.

60. The transmitter as claimed in claim 58 wherein a frequency cutoff of the passive high-pass network is set to be about equal to a bit toggle frequency of the input signal.

61. The transmitter as claimed in claim 58 wherein the passive high-pass network is a continuous-time high pass filter comprising a resistor-capacitor network.

62. The transmitter as claimed in claim 58 wherein the transmitter is to be coupled to a channel having a frequency attenuation, and wherein the passive high-pass network includes a set of high-pass filters configurable to provide a filter transfer function to offset the frequency attenuation.

63. A monolithic semiconductor chip including one or more transmitters as claimed in claim 58.

64. A method comprising:

generating a first signal representing a digital input signal;

generating a second signal representing a high pass filtered version of the digital input signal, the second signal including a spike corresponding to each transition of the digital input signal, each spike in the second signal having a rapid rise or fall from a zero signal level followed by a gradual decay to the zero signal level;

combining the first and second signals to produce an output signal; and

sending the output signal along a signal path to a receiver.

65. The method as claimed in claim 64 wherein the gradual decay follows at least approximately an exponential decay pattern.

66. The method as claimed in claim 64 wherein the signal path has a frequency attenuation, the method further comprising configuring a set of high-pass filters to provide a filter transfer function to offset the frequency attenuation.

67. A method of data transmission comprising the steps of accepting a digital input signal having a plurality of discrete values corresponding to respective ones of a plurality of successive time intervals, and transmitting an output signal having a signal parameter which varies substantially as a combination of:

a first function having one of a plurality of discrete values for each one of a series of data intervals, respective ones of the plurality of discrete values representing respective ones of the plurality of digital values; and

a second function corresponding to a high-pass filtered version of the first function, the second function including a pulse corresponding to each transition in the first function, each pulse including a sharp change from a steady state value of the second function followed by a gradual decay toward the steady state value that follows, at least approximately, an exponential decay pattern.

68. A transmitter comprising:

first driver means for generating a first signal representing a digital input signal;

second driver means for generating a second signal substantially corresponding to a high pass filtered version of the digital input signal, the second signal including a spike corresponding to each transition of the digital input signal, each spike in the second signal having a rapid rise or fall from a zero signal level followed by a gradual decay to the zero signal level; and

means for combining the first and second signals to produce an output signal.