Method for Forming Laterally Extending Dielectric Layer in a Trench-Gate FET

• US 20100029083A1
• Filed: 10/08/2009
• Published: 02/04/2010
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: John Tracey Andrews
• Inventors: Andrews, John Tracey
• Granted Patent: US 7,855,115 B2
• Time in Patent Office: Days
• US Class Current: 438/700
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer inside and outside the trench. The protective layer is partially removed such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer.

Claims

1. A method of forming a FET, comprising:

forming a trench in a silicon region;

forming a silicon nitride layer over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom;

forming a layer of low temperature oxide (LTO) over the silicon nitride layer such that the LTO layer is thicker along the surface of the silicon region adjacent the trench than along the trench bottom; and

uniformly etching back the LTO layer such that a portion of the silicon nitride layer extending along the trench bottom and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the LTO layer.

2. The method of claim 1 further comprising:

removing the exposed portion of the silicon nitride layer along the trench bottom using an anisotropic etch process; and

forming a dielectric layer along the trench bottom using a local oxidation of silicon (LOCOS) process.

3. The method of claim 2 further comprising:

prior to forming the silicon nitride layer, forming a nitride etch resistant layer to protect the silicon region along the trench bottom during the removing step.

4. The method of claim 3 wherein the nitride etch resistant layer comprises pad oxide, and extends over the surface of the silicon region adjacent to the trench and along the trench sidewalls and bottom, wherein the step of removing the exposed portion of the silicon nitride layer exposes a portion of the pad oxide layer extending along the trench bottom.

5. The method of claim 1 wherein the silicon nitride layer is formed using a low pressure chemical vapor deposition (LPCVD) process.

6. A method of forming a FET, comprising:

forming a trench in a semiconductor region;

forming an oxidation barrier layer over a surface of the semiconductor region adjacent the trench and along the trench sidewalls and bottom;

forming a protective layer over the oxidation barrier layer inside and outside the trench;

partially removing the protective layer such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the semiconductor region adjacent the trench remain covered by remaining portions of the protective layer;

removing the exposed portion of the oxidation barrier layer from along the trench bottom; and

thereafter

forming a dielectric layer along the bottom of the trench.

7. The method of claim 6 further comprising:

prior to forming the oxidation barrier layer, forming an insulating layer over the surface of the semiconductor region adjacent to the trench and along the trench sidewalls and bottom, wherein removing the exposed portion of the oxidation barrier layer exposes a portion of the insulating layer extending along the trench bottom.

8. The method of claim 6 wherein the oxidation barrier layer comprises silicon nitride, and the step of removing the exposed portion of the oxidation barrier layer is carried out using an anisotropic etch process.

9. The method of claim 6 wherein the silicon nitride layer is formed using a low pressure chemical vapor deposition (LPCVD) process.

10. The method of claim 6 wherein the dielectric layer is formed using a local oxidation of silicon (LOCOS) process.

11. The method of claim 6 wherein the protective layer comprises low temperature oxide (LTO).

12. The method of claim 6 wherein the portion of the protective layer extending along the surface of the semiconductor region adjacent the trench is thicker than the portion of the protective layer extending along the trench bottom.

13. The method of claim 12 wherein the step of partially removing the protective layer comprises:

uniformly etching the protective layer.