INTEGRATED CIRCUIT CHARACTERISATION SYSTEM AND METHOD

• US 20100030497A1
• Filed: 07/31/2008
• Published: 02/04/2010
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: TechInsights, Inc. (M3, Inc.)
• Original Assignee: Semiconductor Insights Incorporated (Informa PLC)
• Inventors: Sherstyuk, Mykola, Zavadsky, Vyacheslav L.
• Granted Patent: US 7,899,640 B2
• Time in Patent Office: Days
• US Class Current: 702/57
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371

Abstract

There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.

Claims

1. A method of characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, the method comprising the steps of:

executing a test procedure on the IC that invokes the aspect;

invoking at least one operational bottleneck during said executing step to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect;

collecting data generated via said test procedure in response to said bottleneck; and

comparing said system-level operation exhibited by said data for consistency with the pre-defined system-level characteristic.

2. The method according to claim 1, wherein said data comprises side-channel data.

3. The method according to claim 1, wherein said test procedure is executed with the IC operating in an environment conducive to exhibiting a native operation thereof.

4. The method according to claim 1, wherein the pre-defined characteristic is defined by an element of a patent claim relating to IC operation, and wherein said evaluating step comprises evaluating whether operation of the IC is consistent with this patent claim element.

5. The method according to claim 1, wherein said test procedure is executed with the IC operating in an operating system (OS) free environment.

6. The method according to claim 5, wherein operating the integrated circuit in an OS free environment comprises the steps of:

providing an open source operating system;

adjusting said open source operating system to remove at least one parameter that in operation obscures a native operation of the IC; and

executing the revised open source operating system on the IC.

7. The method according to claim 1, wherein the aspect is selected from memory management and power management.

8. The method according to claim 1, wherein said bottleneck is invoked by said test procedure.

9. The method according to claim 1, wherein said bottleneck is invoked distinctly from said test procedure.

10. The method according to claim 1, wherein the characteristic comprises a functional characteristic as defined by a descriptive document.

11. The method according to claim 1, wherein said test procedure comprises a benchmark test.

12. A system for characterizing an integrated circuit (IC) for comparison with a pre-defined characteristic related to an aspect of IC operation, the system comprising:

a computer-readable medium comprising statements and instructions for execution by the system on the IC to implement a test procedure configured to invoke the aspect, while invoking at least one operational bottleneck to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect;

a data storage device for collecting data generated via said test procedure in response to said bottleneck; and

an output for enabling comparison of said system-level operation exhibited by said data for consistency with the pre-defined characteristic.

13. The system of claim 12, further comprising an operating system (OS) configured to enable execution of said test procedure on the IC.

14. The system according to claim 13, wherein said OS is configured to enable execution of said test procedure in an OS-free environment.

15. The system according to claim 13, wherein said OS comprises a Linux-based OS.

16. The system according to claim 13, wherein said OS comprises interrupts disabled.

17. The system according to claim 13, wherein said OS comprises at least one uninitialized peripheral device.

18. The system according to claim 12, wherein said data comprises side-channel data.

19. The system according to claim 12, wherein said test procedure comprises a benchmark test.

20. A computer-readable medium comprising statement and instructions for execution by an integrated circuit (IC) for characterizing same for comparison with a pre-defined characteristic related to an aspect of IC operation in accordance with the following steps of:

executing a test procedure on the IC configured to invoke the aspect;

invoking at least one operational bottleneck during said executing step to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect;

collecting data generated via said test procedure in response to said bottleneck; and

accessing said data to enable comparison of said system-level operation exhibited thereby for consistency with the pre-defined operational characteristic.

21. The computer-readable medium according to claim 21, wherein said data comprises side-channel data.

22. The computer-readable medium according to claim 21, further comprising statements and instructions for executing said test procedure with the IC operating in an operating system (OS) free environment.

23. The computer-readable medium according to claim 23, further comprising statements and instructions wherein operating the IC in an OS free environment comprises executing a revised open source operating system on the IC for which at least one parameter is removed which, in operation, obscures a native operation of the IC.