MEDIA PROCESSING METHOD AND DEVICE

• US 20100030928A1
• Filed: 08/04/2008
• Published: 02/04/2010
• Est. Priority Date: 08/04/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Conroy, David G., Lindahl, Aram, Corlett, Barry, Warren, Niel D., Schell, Steve
• Granted Patent: US 8,041,848 B2
• Time in Patent Office: Days
• US Class Current: 710/23
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G06F 21/1064 Restricting content processing at operating system level
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor.

Claims

1. A hand-held electronic device, comprising:

a host subsystem; and

a media processing subsystem, comprising;

a subsystem interface coupled to the host subsystem, the subsystem interface configured to exchange media data between the host processor and the media processing subsystem; and

a digital signal processor coupled to the subsystem interface, the digital signal processor configured to process the media data received via the subsystem interface and route the media data to an input/output device.

2. The electronic device of claim 1, wherein the media processing subsystem is configured to process audio data and the host subsystem is configured to process video data.

3. The electronic device of claim 2, comprising a timekeeping interface configured to provide time-related information to both the host subsystem and the media processing subsystem, wherein the time-related information is used to synchronize the audio data with the video data.

4. The electronic device of claim 1, wherein at least part of the host subsystem is configured to enter a low power mode while the media processing subsystem is processing the media data.

5. The electronic device of claim 1, wherein the media processing subsystem comprises a telephone communications device coupled to the digital signal processor, the digital signal processor configured to route telephone audio data between the telephone communications device and the input/output device.

6. The electronic device of claim 5, wherein at least part of the host subsystem is configured to enter a low power mode while the media processing subsystem is processing the telephone audio data.

7. The electronic device of claim 5, wherein the digital signal processor is configured to mix telephone audio with audio samples received via the subsystem interface.

8. The electronic device of claim 1, wherein the host subsystem comprises a DMA controller coupled to the subsystem interface, the DMA controller configured to route the media data from the host processor to the subsystem interface.

9. The electronic device of claim 8, wherein the DMA controller is configured to decrypt the media data.

10. The electronic device of claim 8, wherein at least part of the host subsystem is configured to enter a low power mode after causing the DMA controller to conduct a DMA transfer.

11. The electronic device of claim 1, comprising an initialization path that allows the transmission of a trusted program code from the host subsystem to the media processing subsystem, the initialization path configured to be inoperable after the transmission of the trusted program code.

12. A method of processing audio data in a hand-held electronic device, comprising:

sending a quantity of audio data from a host subsystem to an electronic storage in an audio subsystem, the quantity being large enough to allow the host subsystem to profitably enter and exit a low power mode;

entering the host subsystem into the low power mode;

processing the audio data stored in the electronic storage of the audio subsystem; and

sending the processed audio data to an output device coupled to the audio subsystem.

13. The method of claim 12, comprising:

causing the host subsystem to exit the low power mode; and

sending an additional quantity of audio data from the host subsystem to the electronic storage in the audio subsystem, the quantity being large enough to allow the host subsystem to profitably enter and exit the low power state.

14. The method of claim 12, wherein the quantity of audio data sent from the host subsystem to the electronic storage in the audio subsystem provides approximately ten to thirty seconds worth of audio data.

15. A method of processing audio data in a hand-held electronic device, comprising:

loading a first block of audio data into a first memory in a host subsystem;

loading a first DMA transfer instruction into a second memory in the host subsystem, wherein the DMA transfer instruction describes the first block of audio data loaded into the first memory;

entering a central processing unit into a low power state;

transferring a first portion of the audio data in the first memory into an audio subsystem according to the first DMA transfer instruction; and

entering a DMA controller into a low power state.

16. The method of claim 15, comprising:

resuming normal operation of the DMA controller;

transferring a second portion of the audio data in the first memory into the audio subsystem according to the DMA transfer instruction; and

re-entering the DMA controller into the low power state.

17. The method of claim 15, comprising:

resuming normal operation of the central processing unit;

loading a second block of audio data into the first memory;

loading a second DMA transfer instruction into the second memory, wherein the DMA transfer instruction describes the second block of audio data loaded into the first memory; and

re-entering the central processing unit into the low power state.

18. A digital signal processor, comprising:

a core processor, configured to process audio data;

an at least one input buffer coupled to the core processor, the at least one input buffer configured to receive audio data from an at least one audio input device;

an at least one output buffer coupled to the core processor, the at least one output buffer configured to send processed audio data to an at least one audio output device; and

a programmable memory configured to control the routing of small audio data segments from the at least one input buffer to the at least one output buffer.

19. The digital signal processor of claim 18, wherein the programmable memory is configured to assign a priority level to each of the small audio data segments.

20. The digital signal processor of claim 18, wherein the programmable memory is configured to control the routing of audio data from the at least one audio input device to the at least one input buffer.

21. The digital signal processor of claim 18, wherein the programmable memory is configured to control the routing of processed audio data from the at least one output buffer to the at least one audio output device.

22. The digital signal processor of claim 18, wherein the core processor is configured to mix two or more audio samples;

sample rate convert audio data;

equalize audio data;

compress or decompress audio data;

encrypt or decrypt audio data;

or some combination thereof.