NONVOLATILE MEMORY SYSTEM

• US 20100030951A1
• Filed: 10/13/2009
• Published: 02/04/2010
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Application Number:
  US12/578,115
• Publication Number:
  US 20100030951A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade.

Claims

1. A nonvolatile memory system comprising:

a plurality of nonvolatile memory devices in a daisy chain cascade arrangement; and

a nonvolatile memory controller device configured to interface with an external system and control operations of each of the plurality of nonvolatile memory devices by communications through the daisy chain cascade arrangement,

the plurality of nonvolatile memory devices being configured in a bidirectional daisy chain cascade that includes at least first and second paths for carrying signals in first and second directions, respectively.

2. The system of claim 1, wherein each of the first and second paths carries signals in a serial configuration through the daisy chain cascade arrangement.

3. The system of claim 2, wherein each of the first and second paths carries command, data and address signals.

4. The system of claim 3, wherein each of the devices has separate ports coupled to the first and second paths.

5. The system of claim 4, wherein each of the devices has first input and output (I/O) ports and second I/O ports, the first and second I/O ports being coupled to the first and second paths for carrying signals in the first and second directions, respectively, the output port of one device being coupled to the input port of a next device by a link to form either of the first and second paths.

6. The system of claim 1, wherein the plurality of nonvolatile memory devices include Flash memory that is controlled by the memory controller device.

7. The system of claim 1, wherein the memory controller device includes an external system interface and a nonvolatile memory interface, the external system interface configured for communication with an external system and the memory interface coupled to at least one of the plurality of memory devices.

8. The system of claim 1, wherein each of the plurality of nonvolatile memory devices and the memory controller device are implemented in a common support assembly.

9. The system of claim 8, wherein each of the plurality of nonvolatile memory devices and the memory controller device are implemented in separate chips enclosed in a system-in-package enclosure.

10. The system of claim 1, wherein the controller device addresses one of the plurality of memory devices by sending an address through the daisy chain cascade, the plurality of memory devices comparing the address to a device identifier (ID) stored at each of the plurality of devices.

11. The system of claim 10, wherein each of the plurality of memory devices generates a device ID in response to communications between the memory controller device and the plurality of memory devices.

12. The system of claim 11, wherein the memory controller device sends the commands through the daisy chain cascade arrangement with the address, the address corresponding to the device ID of one of the plurality of memory devices.

13. A method of controlling a nonvolatile memory system, the method comprising:

sending a command associated with the communications from the nonvolatile memory controller device to a plurality of nonvolatile memory devices in a daisy chain cascade arrangement through a first path; and

receiving, at the nonvolatile memory controller, data from one of the plurality of nonvolatile memory devices responsive to the command through a second path.

14. The method of claim 13, wherein the plurality of memory devices are configured in a bi-directional daisy chain cascade.

15. The method of claim 14, further comprising sending the command in a serial configuration through the daisy chain cascade arrangement.

16. The method of claim 15, wherein the command is carried by a signal path carrying at least one of data and address signals.

17. The method of claim 16, further comprising addressing one of the plurality of memory devices by sending an address through the daisy chain cascade, the plurality of memory devices comparing the address to a device identifier (ID) stored at each of the plurality of devices.

18. The method of claim 17, further comprising generating a device ID at each of the plurality of memory devices in response to communication with at least one of the memory controller device and another one of the plurality of memory devices.

19. The method of claim 18, further comprising sending the commands through the daisy chain cascade arrangement with the address, the address corresponding to the device ID of one of the plurality of memory devices.

20. The method of claim 19, further comprising receiving a response from the target device through the devices in the second direction.