UNIFIED MEMORY ARCHITECTURE FOR RECORDING APPLICATIONS

• US 20100031123A1
• Filed: 10/12/2009
• Published: 02/04/2010
• Est. Priority Date: 12/12/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Cheng Qian, Rajesh Juluri
• Inventors: Qian, Cheng, Juluri, Rajesh
• Granted Patent: US 7,962,833 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2020/10787 parameters, e.g. for decoding or encoding
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes

Abstract

An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Claims

1. An apparatus comprising:

a first circuit that (i) generates an input signal by reading compressed-and-encoded video from a source while said apparatus is in a first state and a second state, (ii) extracts video data as a first block arranged as a Reed-Solomon product code from said input signal, (iii) sends said first block to an external memory, (iv) calculates a plurality of correction values corresponding to said first block while said first block remains unaltered as initially written in said external memory, (iv) retrieves said first block from said external memory and (v) corrects said first block with said correction values to generate corrected video data in a first internal signal; and

a second circuit that (i) decodes said corrected video data to generate decoded video data while in said first state, (ii) encodes said decoded video data to generated encoded video data in a second internal signal while in said second state, (iii) transfers said first block from said first circuit to said external memory and (iv) transfers said first block from said external memory to said first circuit.

2. The apparatus according to claim 1, wherein said first circuit comprises an error correction code module that generates (i) a plurality of syndromes from said first block and (ii) said correction values from said syndromes.

3. The apparatus according to claim 2, wherein said error correction code module comprises:

a row syndrome module that calculates a plurality of first row syndromes of said syndromes from said first block;

a column syndrome module that calculates a plurality of first column syndromes of said syndromes from said first block;

a decoder module that (a) decodes in a sequence alternating between a first pass and a second pass, wherein (i) said first pass comprises decoding said first column syndromes to generate column correction results and (ii) said second pass comprises decoding said first row syndromes to generate row correction results and (b) generates said correction values based on said syndromes; and

a delta syndrome module that (i) updates said first row syndromes in response to said column correction results and (ii) updates said first column syndromes in response to said row correction results.

4. The apparatus according to claim 3, further comprising a local memory coupled to said row syndrome module, said column syndrome module, said delta syndrome module and said decoder module, wherein said local memory (i) stores both said first row syndromes and said first column syndromes from said first block while said syndromes are being updated, (ii) stores said correction values in place of said syndromes once updating is complete and (iii) excludes said first block.

5. The apparatus according to claim 4, wherein said first circuit further comprising a buffer connected to an output, wherein said buffer (i) stores at least two rows of said first block and (ii) presents said first block one row at a time to both said output and said column syndrome module.

6. The apparatus according to claim 5, wherein said external memory stores said first block as presented from said buffer.

7. The apparatus according to claim 4, wherein said local memory stores both a plurality of second row syndromes and a plurality of second column syndromes from a second block of said input signal substantially simultaneously with storing said first row syndromes and said first column syndromes of said first block.

8. The apparatus according to claim 7, wherein said row syndrome module writes said second row syndromes of said second block substantially simultaneously with said delta syndrome module updating said first row syndromes and said first column syndromes of said first block.

9. The apparatus according to claim 4, further comprising a dispatcher module connected between said local memory and said decoder module, wherein said dispatcher module presents a plurality of decode jobs from said local memory to said decode module based on a corresponding priority of said decode jobs.

10. The apparatus according to claim 9, wherein each of said decode jobs comprises one of (i) decoding said first row syndromes and (ii) decoding said first column syndromes.

11. An apparatus comprising:

a first circuit configured to (i) generate an input signal by reading compressed-and-encoded video from a source while said apparatus is in a first state and a second state, (ii) extract video data as a first block arranged as a Reed-Solomon product code from said input signal, (iii) send said first block to an external memory, (iv) calculate a plurality of first row syndromes and a plurality of first column syndromes from said first block, (v) decode in a sequence alternating between a first pass and a second pass, wherein (a) said first pass comprises decoding said first column syndromes to generate column correction results and (b) said second pass comprises decoding said first row syndromes to generate row correction results, (vi) update said first row syndromes in response to said column correction results, (vii) update said first column syndromes in response to said row correction results, (viii) calculate a plurality of correction values corresponding to said first block, (ix) retrieve said first block from said external memory and (x) correct said first block with said correction values to generate corrected video data in a first internal signal;

a second circuit configured to (i) decompress said corrected video data to generate original video content in an output signal suitable to drive a monitor while in said first state and (ii) encode said corrected video data to generated encoded video data in a second internal signal suitable to write to a drive memory while in said second state wherein said drive memory is different than said source.

12. The apparatus according to claim 11, further comprising a local memory configured to (i) store both said first row syndromes and said first column syndromes and (ii) exclude said first block.

13. The apparatus according to claim 11, wherein said second circuit is further configured to (i) transfer said first block as received from first circuit to said external memory and (ii) transfer said first block as received from said external memory to said first circuit.

14. The apparatus according to claim 11, wherein said first circuit comprises an error correction code module configured to generate (i) said first row syndromes and said first column syndromes from said first block and (ii) said correction values from said syndromes.

15. The apparatus according to claim 14, wherein said error correction code module comprises:

a row syndrome module configured to calculate said first row syndromes from said first block;

a column syndrome module configured to calculate said first column syndromes from said first block;

a decoder module configured to generate said correction results by decoding said first column syndromes and said first row syndromes; and

a delta syndrome module configured to (i) update said first row syndromes in response to said column correction results and (ii) update said first column syndromes in response to said row correction results.

16. The apparatus according to claim 15, wherein said first circuit further comprises a first buffer configured to buffer a plurality of rows from said first block substantially simultaneously with said column syndrome module calculating said first row syndromes.

17. The apparatus according to claim 16, wherein said first buffer is further configured to present said first block one row at a time and substantially simultaneously to (i) said external memory and (ii) said column syndrome module.

18. The apparatus according to claim 11, wherein said first circuit is further configured to store a plurality of second row syndromes and a plurality of second column syndromes of a second block of said input signal in a local memory substantially simultaneously with storing said first row syndromes and said first column syndromes of said first block is said local memory.

19. The apparatus according to claim 11, wherein said first circuit comprises a second buffer configured to (i) receive said first block from said external memory and (ii) generate said corrected video data by correcting said first block with said correction values.

20. An apparatus comprising:

means for (i) generating an input signal by reading compressed-and-encoded video from a source while said apparatus is in a first state and a second state, (ii) extracting video data as a first block arranged as a Reed-Solomon product code from said input signal, (iii) sending said first block to an external memory, (iv) calculating a plurality of correction values corresponding to said first block while said first block remains unaltered as initially written in said external memory, (v) retrieving said first block from said external memory and (vi) correcting said first block with said correction values to generate corrected video data in a first internal signal; and

means for (i) decoding said corrected video data to generated decoded video data while in said first state, (ii) encoding said decoded video data to generated encoded video data in a second internal signal while in said second state, (iii) transferring said first block from said means for sending to said external memory and (iv) transferring said first block from said external memory to said means for retrieving.