BACK CONTACTED SOLAR CELL

• US 20100032011A1
• Filed: 09/27/2007
• Published: 02/11/2010
• Est. Priority Date: 09/29/2006
• Status: Abandoned Application

• Current Assignee: Renewable Energy Corporation ASA
• Original Assignee: Renewable Energy Corporation ASA
• Inventors: SAUAR, Erik
• Application Number:
  US12/443,281
• Publication Number:
  US 20100032011A1
• Time in Patent Office: Days
• US Class Current: 136/256
• CPC Class Codes: H01L 31/02167 for solar cells
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/0682 back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

This invention relates to a cost effective method of producing a back contacted silicon solar cell and the cell made by the method, where the method comprises applying a silicon substrate, wafer or thin film, doped on the back side with alternating P-type and N-type conductivity in an interdigitated pattern and optionally a layer of either P- or N-type on the front side of the wafer, depositing one or more surface passivation layers on both sides of the substrate, creating openings in the surface passivation layers on the back side of the substrate, depositing a metallic layer covering the entire back side and which fills the openings in the surface passivation layers, and creating openings in the deposited metallic layer such that electric insulated contacts with the doped regions on the back side of the substrate is obtained.

Claims

1-16. -16. (canceled)

17. Method for producing a back-contacted solar cell, where the method comprises applying a silicon substrate, wafer or thin film, doped on the back side with alternating P-type and N-type conductivity in an interdigitated pattern and optionally a layer of either P- or N-type on the front side of the wafer,

wherein the method further comprises:

depositing one or more surface passivation layers on the front side and on the back side of the substrate,

the surface passivation layer on the back side comprises an inner amorphous silicon layer or an amorphous silicon carbide layer, the inner layer is followed by a layer of hydrogenated silicon nitride,

creating openings in one or more surface passivation layers on the back side of the substrate,

depositing a metallic layer covering substantially all of the back side and which fills the openings in the surface passivation layers,

creating openings in the deposited metallic layer such that electrically insulated contacts with the doped regions on the back side of the substrate is obtained.

18. Method according to claim 17,

wherein

the openings in the surface passivation layers is only made in the outer silicon nitride layer (7).

19. Method according to claim 17,

wherein

the metallic layer is substantially aluminium or substantially nickel.

20. Method according to claim 17,

wherein

the substrate is heated to a temperature the range of 200-700°

C., preferably in the range of 300-600°

C.

21. Method according to claim 18,

wherein

the inner amorphous silicon layer on the back side of the substrate has a thickness in the range of 1-1000 nm,

the surface passivation layer on the front side comprises an outer silicon nitride layer, said silicon nitride layer has a thickness in the range of 10-200 nm,

the outer hydrogenated silicon nitride layer on the back side of the substrate has a thickness in the range of 10-1000 nm.

22. Method according to claim 20,

wherein

the aluminium layer has a thickness in the range of 1-50 μ

m and is deposited by use of sputtering or evaporation, and

the following heat treatment is performed at a temperature about 500°

C. for four minutes.

23. Method according to claim 17,

wherein the openings in the surface passivation layers are obtained by:

use of an etching agent that is either ink-jet printed or screen-printed onto the region(s) of the outer surface passivation layer on the back side of the substrate,

use of laser to ablate the surface passivation layers, or

screen-printing or ink jet printing a chemical resist covering the areas of the surface passivation layer that are to remain on the back side of the substrate and optionally screen-printing or ink jet printing a chemical resist covering the entire front surface passivation of the substrate followed by at least partial immersion of the substrate in an etching agent to remove the unprotected passivation film(s).

24. A method according to claim 23,

wherein

the chemical etching agent comprises one or more of the following agents;

a solution comprising diluted or concentrated HF, or KOH, or NaOH, or a mixture comprising HF, HNO₃, and CH₃COOH.

25. A method according to claim 21,

wherein the surface passivation of the front and back side of the semiconductor substrate is obtained by:

cleaning the semiconductor substrate by immersion in a mixture of H₂SO₄ and H₂O₂, or a mixture of HCl, H₂O₂ and H₂O, or a mixture of NH₄OH, H₂O₂ and H₂O, removing the oxide film on the substrate sides by immersion in diluted HF,

introducing the substrate into a plasma enhanced chemical vapour deposition chamber (PECVD-chamber), —

depositing a 1-150 nm thick amorphous silicon film on one or both sides of the substrate by use of SiH₄ as sole precursor gas at about 250°

C.,

depositing a 10-200 nm thick silicon nitride film by use of a mixture of SiH₄ and NH₃ as precursor gases at about 250°

C. on top of the one or both amorphous silicon films, and finally

annealing the substrate with the deposited passivation at a temperature about 500°

C. for four minutes.

26. A method according to claim 25,

wherein the annealing is performed after deposition of the metallic layer on top of the silicon nitride layer on the back side of the substrate.

32. Solar cell according to claim 17,

wherein the substrate (1) is either a mono-crystalline, micro-crystalline, or a multi-crystalline silicon wafer, or a silicon thin film of either micro crystalline, multi crystalline or mono crystalline grain quality.

33. Method according to claim 18,

wherein

the metallic layer is substantially aluminium or substantially nickel.

34. Method according to claim 18,

wherein

the substrate is heated to a temperature the range of 200-700°

C., preferably in the range of 300-600°

C.

35. Method according to claim 19,

wherein

the substrate is heated to a temperature the range of 200-700°

C., preferably in the range of 300-600°

C.

36. Method according to claim 19,

wherein

the inner amorphous silicon layer on the back side of the substrate has a thickness in the range of 1-1000 nm,

the surface passivation layer on the front side comprises an outer silicon nitride layer, said silicon nitride layer has a thickness in the range of 10-200 nm,

the outer hydrogenated silicon nitride layer on the back side of the substrate has a thickness in the range of 10-1000 nm.

27. A solar cell comprising:

a silicon substrate (1) doped in a layer (3) on the back side with alternating P-type and N-type conductivity in an interdigitated pattern and optionally a layer (2) of either P- or N-type on the front side of the substrate (1),

one or more surface passivation layers (4, 5) on the front side of the substrate (1), wherein it further comprises;

one or more surface passivation layers (6,7) on the back side of the substrate (1),

the inner surface passivation layer (6) is an amorphous silicon layer or an amorphous silicon carbide layer, the inner layer is followed by a layer of hydrogenated silicon nitride,

at least one opening (8) in one or more surface passivation layers (6, 7) for each doped region of the layer (3), and

a metallic contact (9) filling each opening (8) to obtain electric contact with the underlying doped region in the layer (3) of the substrate (1).

28. Solar cell according to claim 27,

wherein

the metallic layer is substantially aluminium or substantially nickel.

29. Solar cell according to claim 27,

wherein

the inner amorphous silicon layer on the back side of the substrate has a thickness in the range of 1-1000 nm,

the surface passivation layer on the front side comprises an outer silicon nitride layer, said silicon nitride layer has a thickness in the range of 10-200 nm,

the outer hydrogenated silicon nitride layer on the back side of the substrate has a thickness in the range of 10-1000 nm.

30. Solar cell according to claim 27,

wherein

the metallic contacts (9) have a thickness as measured perpendicular on the surface passivation layers in the range of 1-50 μ

m.

31. Solar cell according to claim 27,

wherein

the openings (8) in the surface passivation layers has only been made in the outer surface passivation layers (7) on the back side of the substrate (1), and

the electric contact with the doped regions below the amorphous silicon layer (6) is obtained by heating the substrate until the aluminium phase (8) re-crystallises the in-between lying amorphous silicon layer (6) and forms connection points (10).