SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100032667A1
• Filed: 08/05/2009
• Published: 02/11/2010
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYANAGA, Akiharu, AKIMOTO, Kengo, YAMAZAKI, Shunpei, MIYAIRI, Hidekazu, SHIRAISHI, Kojiro
• Granted Patent: US 8,115,201 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.

Claims

1. A semiconductor device including a thin film transistor, the thin film transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a source electrode layer and a drain electrode layer over the gate insulating layer;

a first buffer layer having n-type conductivity over the source electrode layer;

a second buffer layer having n-type conductivity over the drain electrode layer; and

an oxide semiconductor layer over the first and second buffer layers,

wherein the oxide semiconductor layer overlapping with the gate electrode layer is partly over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer,

wherein a carrier concentration of the first buffer layer and the second buffer layer is higher than a carrier concentration of the oxide semiconductor layer, and

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the first buffer layer interposed therebetween, and

wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the second buffer layer interposed therebetween.

2. The semiconductor device according to claim 1, wherein the first and second buffer layers include an impurity element imparting n-type conductivity.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a carrier concentration less than 1×

10¹⁷ atoms/cm³, and the first and second buffer layers have a carrier concentration of 1×

10¹⁸ atoms/cm³ or more.

4. The semiconductor device according to claim 1, further comprising:

a third buffer layer between the oxide semiconductor layer and the first buffer layer; and

a forth buffer layer between the oxide semiconductor layer and the second buffer layer,

wherein the third buffer layer has a carrier concentration higher than that of the oxide semiconductor layer and lower than that of the first buffer layer, and

wherein the forth buffer layer has a carrier concentration higher than that of the oxide semiconductor layer and lower than that of the second buffer layer.

5. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer contain titanium.

6. The semiconductor device according to claim 1, wherein a side surface of the source electrode layer opposite to a side surface of the drain electrode layer is covered with the first buffer layer,

wherein the side surface of the drain electrode layer opposite to the side surface of the source electrode layer is covered with the second buffer layer.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

8. The semiconductor device according to claim 1, wherein the first and second buffer layers contain indium, gallium, and zinc.

9. The semiconductor device according to claim 1, wherein the first and second buffer layers contain magnesium, aluminum, or titanium.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a source electrode layer and a drain electrode layer over the gate insulating layer;

forming a buffer layer having n-type conductivity over the source electrode layer and the drain electrode layer; and

forming an oxide semiconductor layer over the buffer layer,

wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the oxide semiconductor layer, and

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the buffer layer interposed therebetween.

11. The method for manufacturing a semiconductor device, according to claim 10, wherein the oxide semiconductor layer is partly over and in contact with the gate insulating layer overlapping with the gate electrode layer and is provided between the source electrode layer and the drain electrode layer.

12. The method for manufacturing a semiconductor device, according to claim 10, wherein the oxide semiconductor layer has a carrier concentration less than 1×

10¹⁷ atoms/cm³, and the buffer layer has a carrier concentration of 1×

10¹⁸ atoms/cm³ or more.

13. The method for manufacturing a semiconductor device, according to claim 10, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

14. The method for manufacturing a semiconductor device, according to claim 10, wherein the buffer layer contains indium, gallium, and zinc.

15. The method for manufacturing a semiconductor device, according to claim 10, wherein the buffer layer contains magnesium, aluminum, or titanium.