SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20100032711A1
• Filed: 12/29/2008
• Published: 02/11/2010
• Est. Priority Date: 08/11/2008
• Status: Abandoned Application

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Aono, Shinji, Moritani, Junichi
• Application Number:
  US12/344,947
• Publication Number:
  US 20100032711A1
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A p-type region is provided on a first n-type region. A second n-type region is provided on the p-type region, spaced apart from the first n-type region by the p-type region. A gate electrode serves to form an n-channel between the first and second n-type regions. A first electrode is electrically connected to each of the p-type region and the second n-type region. A second electrode is provided on the first n-type region such that it is spaced apart from the p-type region by the first n-type region and at least a part thereof is in contact with the first n-type region. The second electrode is made of any of metal and alloy and serves to inject holes into the first n-type region.

Claims

1. A semiconductor device, comprising:

a first n-type region;

a p-type region provided on said first n-type region;

a second n-type region provided on said p-type region, spaced apart from said first n-type region by said p-type region;

a gate electrode provided on said p-type region with a gate insulating film being interposed, for forming an n-channel between said first and second n-type regions;

a first electrode electrically connected to each of said p-type region and said second n-type region; and

a second electrode provided on said first n-type region such that the second electrode is spaced apart from said p-type region by said first n-type region and at least a part of the second electrode is in contact with said first n-type region, said second electrode being made of any of a metal and an alloy and serving to inject holes into said first n-type region.

2. The semiconductor device according to claim 1, wherein

said second electrode has a work function not lower than 4.8 eV.

3. The semiconductor device according to claim 1, wherein

said second electrode includes a platinum silicide layer.

4. The semiconductor device according to claim 1, wherein

no region made of a p-type semiconductor is provided between said second electrode and said first n-type region.

5. The semiconductor device according to claim 1, wherein

said gate electrode has a trench gate structure.

6. The semiconductor device according to claim 1, wherein

said p-type region includes

a first p-type region located on a side of said first n-type region, and

a second p-type region located on a side of said first electrode and being higher in concentration than said first p-type region.

7. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a semiconductor substrate having a first n-type region,

forming a p-type region on said first n-type region;

forming a second n-type region on said p-type region such that the second n-type region is spaced apart from said first n-type region by said p-type region;

forming, on said p-type region with a gate insulating film being interposed, a gate electrode for forming an n-channel between said first and second n-type regions;

forming a first electrode such that the first electrode is electrically connected to each of said p-type region and said second n-type region; and

forming, on said first n-type region, a second electrode made of any of a metal and an alloy, for injecting holes into said first n-type region, such that the second electrode is spaced apart from said p-type region by said first n-type region and at least a part of the second electrode is in contact with said first n-type region.

8. The method of manufacturing a semiconductor device according to claim 7, wherein

said second electrode has a work function not lower than 4.8 eV.

9. The method of manufacturing a semiconductor device according to claim 7, wherein

said second electrode includes a platinum silicide layer.

10. The method of manufacturing a semiconductor device according to claim 9, wherein

said first n-type region includes silicon, and

said step of forming a second electrode includes the steps of forming a metal layer including platinum on said first n-type region, and forming said platinum silicide layer by causing platinum included in said metal layer and silicon included in said n-type region to react with each other.

11. The method of manufacturing a semiconductor device according to claim 9, wherein

said step of forming a second electrode includes the step of depositing said platinum silicide layer on said first n-type region with any of a vapor deposition method and a sputtering method.

12. The method of manufacturing a semiconductor device according to claim 7, wherein

no region made of a p-type semiconductor is formed between said second electrode and said first n-type region.

13. The method of manufacturing a semiconductor device according to claim 7, wherein

said step of forming a gate electrode includes the steps of

forming a trench having an inner surface at which each of said first and second n-type regions and said p-type region is exposed,

forming said gate insulating film so as to cover said inner surface, and

forming said gate electrode on said gate insulating film.

14. The method of manufacturing a semiconductor device according to claim 7, wherein

said step of forming a p-type region includes the steps of forming a first p-type region on said first n-type region and forming a second p-type region higher in concentration than said first p-type region above said first n-type region, and

said step of forming a first electrode is performed by forming said first electrode such that the first electrode is electrically connected to each of said second p-type region and said second n-type region.