SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100032747A1
• Filed: 07/21/2009
• Published: 02/11/2010
• Est. Priority Date: 08/08/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ariyoshi, Keiko, OKAMURA, Takayuki
• Application Number:
  US12/506,534
• Publication Number:
  US 20100032747A1
• Time in Patent Office: Days
• US Class Current: 257/326
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film, a control gate, an impurity diffusion layer functioning as a source or a drain, and a plurality of barrier films formed on a side surface of the gate electrode section so as to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate. The device further includes a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cell transistors each comprising a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed on the charge accumulation layer using a material with a higher dielectric constant than the gate insulating film, and a control gate formed on the first insulating film, and an impurity diffusion layer as a source or a drain;

a plurality of barrier films formed on a side surface of the gate electrode section to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate; and

a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors;

wherein during annealing of the plurality of memory cell transistors, the plurality of barrier films prevent atoms comprising the second insulating film and the control gate from diffusing to the first insulating film.

2. The semiconductor memory device according to claim 1, wherein the charge accumulation layer is an insulating film, and is one of SiN and a stacked film of SiN and one of HfAlO, HfON, HfSiN, and Al₂O₃.

3. The semiconductor memory device according to claim 1, wherein the charge accumulation layer is also formed between the gate electrode sections of the adjacent ones of the plurality of memory cell transistors.

4. The semiconductor memory device according to claim 1, wherein the first insulating film is one of crystallized LaAlO and Al-rich amorphous LaAlO, and the plurality of barrier films are Al₂O₃.

5. The semiconductor memory device according to claim 1, wherein the first insulating film is amorphous LaAlO, and the plurality of barrier films are Al₂O₃ with a thickness of at least 4 nm.

6. The semiconductor memory device according to claim 1, wherein at least one of the plurality of barrier films which is formed between the first insulating film and the control gate is a metal film.

7. A semiconductor memory device comprising:

a plurality of memory cell transistors each comprising a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed on the charge accumulation layer using a material with a higher dielectric constant than the gate insulating film, and a control gate formed on the first insulating film, and an impurity diffusion layer as a source or a drain;

a first barrier film formed on a side surface of each gate electrode section to cover a side surface of at least the first insulating film;

a second barrier film formed between the first insulating film and the control gate; and

a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors;

wherein the first and second barrier films prevent diffusion of an electric field traveling from the control gate to the gate insulating film.

8. The semiconductor memory device according to claim 7, wherein the charge accumulation layer is an insulating film, and is one of SiN and a stacked film of SiN and one of HfAlO, HfON, HfSiN, and Al₂O₃.

9. The semiconductor memory device according to claim 7, wherein the charge accumulation layer is also formed between the gate electrode sections of the adjacent ones of the plurality of memory cell transistors.

10. The semiconductor memory device according to claim 7, wherein the first insulating film is one of crystallized LaAlO and Al-rich amorphous LaAlO, and the second barrier film is Al₂O₃.

11. The semiconductor memory device according to claim 7, wherein the first insulating film is formed of amorphous LaAlO, and the second barrier film is Al₂O₃ with a thickness of at least 4 nm.

12. The semiconductor memory device according to claim 7, wherein the first barrier film is one of Ta, TaN, W, WN_x, Pt, RuO, Ti, TiNTi₃Al, Ti₂AlN, Ni, Hf, Nb, Mo, RuO₂, Ir, Co, or Cr.

13. A semiconductor memory device manufacturing method comprising:

forming a charge accumulation layer on a semiconductor substrate via a gate insulating film;

forming a first insulating film on the charge accumulation layer and a dielectric of the first insulating film is higher than that of the gate insulating film;

forming a barrier film on the first insulating film;

forming a conductive film on the barrier film;

patterning the conductive film, the barrier film, and the first insulating film to form a gate electrode section;

injecting an impurity into a surface of the semiconductor substrate to form a source and a drain, thus forming a memory cell transistor;

forming a second insulating film on a side surface of the first insulating film in the gate electrode section;

forming a third insulating film covering the memory cell transistor, on the semiconductor substrate; and

annealing the memory cell transistor after forming the second insulating film.

14. The method according to claim 13, wherein the forming a charge accumulation layer is used by off-axis sputtering.

15. The method according to claim 13, wherein the charge accumulation layer is also formed between the gate electrode sections of the adjacent ones of the plurality of memory cell transistors.

16. The method according to claim 13, wherein the first insulating film is one of crystallized LaAlO and Al-rich amorphous LaAlO, and a second insulating film is Al₂O₃.

17. The method according to claim 13, wherein the first insulating film is formed of amorphous LaAlO, and a second insulating film is formed of Al₂O₃ with a thickness of at least 4 nm.

18. The method according to claim 16, wherein the Al₂O₃ is formed using an atomic layer deposition (ALD) method.

19. The method according to claim 15 further comprising;

anisotropic etching the second insulating film using the charge accumulation layer as an etching stopper after forming the second insulating film.