SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

• US 20100032815A1
• Filed: 04/29/2009
• Published: 02/11/2010
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Youn, SungHo, Lee, Jeong, An, JaeSeon, Cha, SangJin
• Granted Patent: US 8,410,584 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit; (2) a semiconductor device disposed adjacent to the upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body. A periphery of the package body is laterally recessed, such that a connection surface of the grounding element is electrically exposed and electrically connected to the EMI shield. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a substrate unit including

an upper surface,

a lower surface, and

a grounding element disposed adjacent to a periphery of the substrate unit and at least partially extending between the upper surface and the lower surface of the substrate unit, the grounding element including a connection surface disposed adjacent to the upper surface of the substrate unit;

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, a periphery of the package body being laterally recessed with respect to the periphery of the substrate unit, such that the connection surface of the grounding element is electrically exposed, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

2. The semiconductor device package of claim 1, wherein the grounding element corresponds to a grounding via, the grounding via includes a via pad disposed adjacent to the upper surface of the substrate unit, and the connection surface of the grounding element corresponds to an electrically exposed surface of the via pad.

3. The semiconductor device package of claim 2, wherein the substrate unit further includes electrical interconnect disposed between the upper surface and the lower surface of the substrate unit, and the grounding via extends between the upper surface of the substrate unit and the electrical interconnect.

4. The semiconductor device package of claim 1, wherein a height of the grounding element is in the range of 0.1 mm to 1.5 mm.

5. The semiconductor device package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along a peripheral portion of the upper surface of the substrate unit.

6. The semiconductor device package of claim 5, wherein the lateral portion terminates substantially at the periphery of the substrate unit.

7. A semiconductor device package, comprising:

a substrate unit including

a first surface,

a second opposing surface, and

a grounding element at least partially extending between the first surface and the second opposing surface of the substrate unit the grounding element corresponding to a remnant of a grounding via and including a connection surface disposed adjacent to a peripheral portion of the first surface of the substrate unit;

a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the first surface of the substrate unit and covering the semiconductor device, a periphery of the package body being recessed with respect to a periphery of the substrate unit, such that the connection surface of the grounding element is electrically exposed adjacent to the peripheral portion of the first surface of the substrate unit, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element.

8. The semiconductor device package of claim 7, wherein the grounding element includes a via pad remnant and a plated channel remnant, the via pad remnant is disposed adjacent to the first surface of the substrate unit, and the plated channel remnant at least partially extends between the first surface and the second opposing surface of the substrate unit.

9. The semiconductor device package of claim 7, wherein the peripheral portion of the first surface of the substrate unit is curved so as to define a cut-out portion of the substrate unit.

10. The semiconductor device package of claim 7, wherein the substrate unit further includes a lateral surface extending between the first surface and the second opposing surface of the substrate unit, the exterior surfaces of the package body include a lateral surface, and the lateral surface of the package body is laterally recessed with respect to the lateral surface of the substrate unit.

11. The semiconductor device package of claim 7, wherein the electromagnetic interference shield is a conformal shield that includes at least one of aluminum, copper, chromium, tin, gold, silver, stainless steel, and nickel.

12. The semiconductor device package of claim 7, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer, and the first layer and the second layer include different electrically conductive materials.

13. A method of forming a semiconductor device package, comprising:

providing a substrate including an upper surface, a lower surface, and grounding vias at least partially extending between the upper surface and the lower surface of the substrate;

electrically connecting a semiconductor device to the upper surface of the substrate;

applying a molding material to the upper surface of the substrate to form a molded structure covering the grounding vias and the semiconductor device;

forming a first set of cutting slits extending through the molded structure, such that;

(a) the molded structure is sub-divided to form a package body covering the semiconductor device, the package body including lateral surfaces defining a periphery of the package body; and

(b) portions of the grounding vias are disposed beyond the periphery of the package body and include connection surfaces;

forming an electromagnetic interference coating adjacent to the package body and the connection surfaces; and

forming a second set of cutting slits extending through the electromagnetic interference coating and the substrate, such that;

(a) the electromagnetic interference coating is sub-divided to form an electromagnetic interference shield disposed adjacent to the package body and the connection surfaces;

(b) the substrate is sub-divided to form a substrate unit including an upper surface, the semiconductor device disposed adjacent to the upper surface of the substrate unit; and

(c) the connection surfaces are disposed adjacent to a peripheral portion of the upper surface of the substrate unit.

14. The method of claim 13, wherein a via size of at least one of the grounding vias is in the range of 50 μ

m to 300 μ

m, and a via pad size of at least one of the grounding vias is in the range of 100 μ

m to 600 μ

m.

15. The method of claim 13, wherein a spacing between nearest-neighbor ones of the grounding vias is in the range of 0.1 mm to 3 mm.

16. The method of claim 13, wherein forming the first set of cutting slits includes performing front-side singulation with respect to an upper surface of the molded structure.

17. The method of claim 13, wherein a width of at least one of the first set of cutting slits is in the range of 100 μ

m to 2,000 μ

m.

18. The method of claim 13, wherein forming the second set of cutting slits includes performing back-side singulation with respect to the lower surface of the substrate.

19. The method of claim 13, wherein a width of at least one of the second set of cutting slits is in the range of 100 μ

m to 600 μ

m.

20. The method of claim 13, wherein the second set of cutting slits is aligned with respect to the first set of cutting slits, and a width of at least one of the second set of cutting slits is less than a width of at least one of the first set of cutting slits.