Field effect transistor and electric circuit

• US 20100033213A1
• Filed: 10/04/2007
• Published: 02/11/2010
• Est. Priority Date: 10/06/2006
• Status: Active Grant

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Fix, Walter, Ullmann, Andreas
• Granted Patent: US 8,217,432 B2
• Time in Patent Office: Days
• US Class Current: 326/112
• CPC Class Codes: H10K 10/471 the gate dielectric comprising only organic materials
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/135 using ink-jet printing

Abstract

The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer.

Claims

1. A field effect transistor comprising;

at least one source electrode layer and a plurality of drain electrode layers arranged in the same plane;

a semiconductor layer overlying the at least one source electrode layer and the plurality of drain electrode layers;

an insulator layer overlying the semiconductor layer; and

a gate electrode layer on the insulator layer characterized in that the gate electrode layer, wherein as seen perpendicular to the plane of the at least one source electrode layer and the plurality of drain electrode layers the gate electrode layers is juxtaposed with only a portion of the source electrode layer and only a portion of the plurality of drain electrode layers such that only the portion of the source electrode layer and portion of the plurality of the drain electrode layers that are juxtaposed with the gate electrode layer are electrically operative as a transistor.

2. The field effect transistor as claimed in claim 1 further including a channel between the at least one source electrode layer and plurality of drain electrode layers wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the plurality of drain electrode layers, covers an area of about 10% to about 90% of the channel.

3. The field effect transistor as claimed in claim 1 wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the plurality of drain electrode layers, covers an area of about 25% to about 50% of the channel.

4. The field effect transistor as claimed in claim 1 wherein the gate electrode layer is one of a bottom gate electrode or a top gate electrode.

5. The field effect transistor as claimed in claim 1 wherein the field effect transistor comprises at least one organic functional layer.

6. The field effect transistor as claimed in claim 5 wherein at least one organic functional layer is formed by printing.

7. The field effect transistor as claimed in claim 5 wherein at least one of the semiconductor layer and the insulator layer is an organic functional layer.

8. The field effect transistor as claimed in claim 1 wherein the source electrode layer, the plurality of drain electrode layers, the semiconductor layer, the insulator layer and the gate electrode layer are on a carrier substrate.

9. The field effect transistor as claimed in claim 8 wherein the carrier substrate is a flexible plastic film selected from one of the group consisting of polyester, polyethylene, polyethylene terephthalate and polyimide.

10. A logic component having including at least one field effect transistor as claimed in claim 1.

11. The logic component as claimed in claim 10 wherein the logic component is a structural element selected from one of the group consisting of inverter components, NOR gates, NAND gates, AND gates and OR gates.

12. The logic component as claimed in claim 11 wherein the logic component comprises an inverter component comprising said field effect transistor and at least one charging component having at least one first electrode and at least one second electrode, wherein the at least one second electrode is arranged for connection to a supply voltage, and wherein the at least one first electrode comprises a plurality of electrodes wherein at least one of the plurality of electrodes is electrically conductively connected to said plurality of drain electrode layers of the field effect transistor which, as seen perpendicular to the plane of the at least one source electrode layer and the plurality of drain electrode layers overlaps at least a portion of the gate electrode layer.

13. The logic component as claimed in claim 12 wherein the electrically conductive connection between the at least one first electrode and the plurality of drain electrode layers of the field effect transistor is formed by at least one of an interconnect via.

14. The logic component as claimed in claim 12 wherein the inverter component field effect transistor has at least one source electrode layer and at least two drain electrode layers and the at least one charging component comprises at least two charging components having at least two first electrodes, wherein a respective one of the at least two drain electrode layers is electrically conductively connected to a respective one of the first electrodes.

15. The logic component of claim 10 including an electronic circuit comprising a plurality of electronic components electrically coupled to the logic component of claim 10 to form said circuit.

16. The logic component of claim 15, wherein the electronic circuit comprises at least two inverter components.

20. The logic component as claimed in claim 15 on a carrier substrate, wherein at least one first component of the plurality of components comprises field effect transistor as claimed in claim 1 and at least two second components each comprising an electrically conductive functional layer and is on the carrier substrate, the plurality of drain electrode layers of the first component is electrically conductively connected to the electrically conductive functional layer of one of the at least two second components by a printed interconnect such that, at least one unused, surplus second component is present.

21. The logic component as claimed in claim 20 wherein the interconnect is printed in a given printing direction such that the at least two second components are arranged serially one after another and adjacent to one another in a direction defined by the printing direction of the interconnect.

22. The logic component as claimed in claim 20 wherein at least two first components are formed, and in that one of the first components is electrically conductively connected to one of the second components by the interconnect, such that at least one first component and at least one second component are present in unused and surplus fashion.

23. The logic component as claimed in claim 22 wherein the interconnect is printed in a given printing direction such that the at least two first components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.

24. The electric circuit as claimed in claim 20 wherein a charging component having at least one first electrode forms an electrically conductive functional layer and at least one second electrode forms a second component, wherein the at least one second electrode is arranged for connection to a supply voltage.

25. A method for producing a logic component as claimed in claim 20 on a carrier substrate comprising:

forming a carrier substrate;

forming at least one first component having a drain electrode and at least two second components on the substrate, each component having an electrically conductive functional layer; and

printing an electrically conductive interconnect in a given direction to electrically conductively connect the at least one first component drain electrode to one of the at least two second component electrically conductive functional layer to one another;

such that the at least one first component, depending on the registration tolerance during the printing of the interconnect to the drain electrode and to the one of the at least two second components, is selectively connected to one or the other of the at least two second components such that at least one second component remains unconnected to the interconnect and unused.

26. The method as claimed in claim 25 including arranging the at least two second components serially one after another and adjacent to one another in the given printing direction of the interconnect.

27. The method as claimed in claim 25 wherein the forming the first component comprises forming at least two first components, and electrically connecting one of the first components to one of the second components by the interconnect, such that at least one first component and at least one second component remain unconnected and unused.

28. The method as claimed in claim 27 comprising forming the at least two first components serially are arranged one after another and adjacent to one another in the given printing direction of the interconnect.

17. The logic component as claimed in claim wherein a first inverter component of the at least two inverter components has a first gate electrode layer, wherein the first gate electrode layer is electrically conductively connected to at least one of at least one interconnect and at least one via of a second inverter component of the at least two inverter components which interconnect and via electrically conductively connects the plurality of drain electrode layers and at least one first electrode of a charging component of the second inverter component.

18. The logic component as claimed in claim 17 wherein the at least one interconnect is in the plane of the at least one source electrode layer and the plurality of drain electrode layers, and wherein the first gate electrode layer and the at least one interconnect are electrically conductively connected to one another by at least one via in the semiconductor layer and the insulator layer.

19. The logic component as claimed in claim 17 wherein the first gate electrode layer is electrically conductively connected to the plurality of drain electrode layers and the at least one first electrode of the second inverter component (101′

) by means of at least one via in the semiconductor layer and the insulator layer.