Level Shifter, Standard Cell, System And Method For Level Shifting

• US 20100033224A1
• Filed: 08/11/2008
• Published: 02/11/2010
• Est. Priority Date: 08/11/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: ACHARYA, Pramod
• Granted Patent: US 7,880,526 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

Implementations are presented herein that include a level shifter circuit.

Claims

1. A level shifter circuit, comprising:

an input node;

an internal node; and

a capacitor having at least two terminals, wherein at least a first terminal of the at least two terminals is coupled to the input node and at least a second terminal of the at least two terminals is coupled to the internal node,

wherein the level shifter circuit is formed in one well.

2. The level shifter circuit of claim 1, wherein the capacitor is a bootstrapping capacitor configured to provide a voltage level at the input node to the internal node.

3. The level shifter circuit of claim 1, further comprising an output node, the output node configured to provide an output signal having low and high voltage states, and wherein the input node is configured to receive an input signal having low and high voltage states, and further wherein a voltage level of the high voltage state of the output signal is different than a voltage level of the high voltage state of the input signal.

4. The level shifter circuit of claim 3, wherein the voltage level of the high voltage state of the input signal corresponds to a first supply voltage and the voltage level of the high voltage state of the output signal corresponds to a second supply voltage.

5. The level shifter circuit of claim 3, wherein a voltage level of the low voltage state of the output signal and a voltage level of the low voltage state of the input signal correspond to a reference potential.

6. The level shifter circuit of claim 1, further comprising a latch circuit coupled to the input node, wherein the input node is configured to receive an input signal, and the latch circuit is configured to provide a non-inverted signal at a non-inverted terminal and an inverted signal at an inverted terminal in response to a logic state of the input signal.

7. The level shifter circuit of claim 6, wherein the internal node of the level shifter circuit is coupled to the non-inverted terminal of the latch circuit.

8. The level shifter circuit of claim 6, further comprising an output node, wherein the output node is coupled to the inverted terminal or the non-inverted terminal of the latch circuit.

9. The level shifter circuit of claim 6, further comprising an output stage coupled to the latch circuit, wherein the output stage is configured to provide an output signal in response to the logic state of the input signal.

10. The level shifter circuit of claim 6, wherein a voltage level of a high voltage state of the input signal corresponds to a first supply voltage and the latch circuit is coupled to a second supply voltage.

11. The level shifter circuit of claim 6, further comprising a first switch device configured to provide a reference potential to the inverted terminal of the latch circuit in response to the logic state of the input signal.

12. The level shifter circuit of claim 6, further comprising a second switch device configured to provide a voltage level at the input node to the non-inverted terminal of the latch circuit in response to a logic state of the inverted terminal of the latch circuit.

13. A level shifter circuit for shifting a voltage level of a signal from a first supply voltage to a second supply voltage, comprising:

an input terminal configured to receive an input signal having low and high voltage states from a first supply voltage domain;

an output terminal configured to provide an output signal having low and high voltage states to a second supply voltage domain;

an internal node; and

a capacitor coupled between the input terminal and the internal node to provide a voltage level at the input terminal to the internal node,

wherein the level shifter circuit is formed in one well of a semiconductor substrate.

14. The level shifter circuit of claim 13, further comprising a latch circuit coupled to the input terminal, wherein the latch circuit is configured to provide a non-inverted signal at a first terminal and an inverted signal at a second terminal in response to a logic state of the input signal.

15. The level shifter circuit of claim 14, wherein the output terminal is coupled to the first terminal or the second terminal of the latch circuit.

16. A standard cell, comprising:

an input node configured to receive an input signal having low and high voltage states, wherein a voltage level of the high voltage state corresponds to a first supply voltage;

an output node configured to provide an output signal having low and high voltage states, wherein a voltage level of the high voltage state corresponds to a second supply voltage;

an internal node; and

a capacitor having at least two terminals, wherein at least a first terminal of the at least two terminals is coupled to the input node and at least a second terminal of the at least two terminals is coupled to the internal node,

wherein the standard cell is formed in one well.

17. A method for level shifting in a level shifter circuit, comprising:

receiving an input signal;

providing a voltage level of the input signal to a boosted node; and

providing an output signal in response to a voltage level of the boosted node,

wherein the level shifter circuit is formed in one well.

18. The method of claim 17, wherein the voltage level of the input signal is provided to the boosted node by using a capacitor coupled between the boosted node and an input node configured to receive the input signal.

19. The method of claim 17, wherein a voltage level of a high voltage state of the output signal is different than a voltage level of a high voltage state of the input signal or wherein a voltage level of a low voltage state of the output signal is different than a voltage level of a low voltage state of the input signal.

20. The method of claim 17, further comprising latching a non-inverted logic state of the input signal in a non-inverted node and latching an inverted logic state of the input signal in an inverted node in response to a logic state of the input signal.

21. The method of claim 20, further comprising switching a reference potential to the inverted node in response to the logic state of the input signal.

22. The method of claim 20, further comprising switching a voltage level at the input node to the non-inverted node in response to a logic state of the inverted node.

23. A system, comprising:

a first voltage domain including a first circuit;

a second voltage domain including a second circuit; and

a level shifter circuit configured to receive an input signal from the first circuit at an input node and to provide an output signal to the second circuit at an output node, wherein the level shifter circuit comprises;

an internal node; and

a capacitor having at least two terminals, wherein at least a first terminal of the at least two terminals is coupled to the input node and at least a second terminal of the at least two terminals is coupled to the internal node,

wherein the level shifter circuit is formed in one well of a semiconductor substrate.

24. The system of claim 23, wherein the first circuit, the second circuit and the level shifter circuit are formed within an integrated circuit device.

25. The system of claim 23, wherein a first supply voltage of the first voltage domain or a second supply voltage of the second voltage domain is dynamically variable.