Level shifter with output spike reduction

• US 20100033226A1
• Filed: 07/17/2009
• Published: 02/11/2010
• Est. Priority Date: 07/18/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Englekirk, Robert Mark, Kelly, Dylan J., Kim, Tae Youn
• Granted Patent: US 9,030,248 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters
• CPC Class Codes: H03K 19/0185 using field effect transistors only

Abstract

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Claims

1. A level shifter apparatus having at least one level-shifted final output ranging from about a positive supply voltage VDD in one state to about a negative supply voltage VSS in another state, either of the two states selectable under control of an input control signal operating within a range substantially different from the range VSS to VDD, the level shifter comprising:

a) a high-level source drive circuit and a low-level source drive circuit configured to output a high-level supply and a low-level supply, respectively, to a final output driver that produces therefrom a level-shifted final output, wherein during each static condition of either of the two states one of the two source drive circuit outputs is “

at a rail”

of either about VSS or about VDD and the other of the two source drive circuit outputs is “

at common”

at about common voltage; and

b) “

away from common”

transition delay circuitry configured to delay a transition of a source drive output from “

at common”

toward a rail until after a different delay-control source drive output has significantly transitioned from “

at a rail”

toward common.

2. The level shifter of claim 1, further comprising two differential final output drivers each producing a level-shifted final output inverted with respect to the other and each coupled to a high-side supply source via a corresponding high-side supply source driver and to a low-side supply source via a corresponding low-side source driver.

3. The level shifter of claim 2, further comprising “

away from common”

transition delay circuitry for each supply source driver configured to delay, after a state change initiated by an input change, initiation of transitions of each supply source driver output from “

at common”

toward a rail until after a delay-control supply source driver output has significantly transitioned from “

at a rail”

toward common.

4. The level shifter of claim 3, wherein each supply source driver output is coupled to a corresponding final output driver, and wherein the delay-control supply source driver output is coupled to a final output driver different from the final output driver coupled to the supply source driver output delayed thereby.

5. The level shifter of claim 3, wherein each supply source driver output is coupled to a corresponding final output driver, and wherein the delay-control supply source driver output is coupled to the same final output driver coupled to the supply source driver output delayed thereby.

6. The level shifter of claim 1, wherein each supply source drive output is coupled to a corresponding final output driver, and wherein the delay-control supply source driver output is coupled to the same final output driver coupled to the supply source driver output delayed thereby.

7. The level shifter of claim 1 comprising two stages, wherein the final output is produced from a second stage that is controlled by a level shifter front end stage having two pairs of intermediate drive source signals, each pair including a high-side intermediate drive source signal that approximates VDD in a first static state and approximates common in the opposite static state, and a low-side intermediate drive source signal that approximates common in the first static state and approximates VSS in the opposite static state, further comprising significant non-parasitic capacitance disposed between the high-side intermediate drive source signal and the low-side intermediate drive source signal of each pair.

8. The level shifter of claim 1 comprising two stages, wherein the final output is produced from a second stage that is controlled by a level shifter front end stage having two pairs of intermediate drive source signals, each pair including a high-side intermediate drive source signal that approximates VDD in a first static state and approximates common in the opposite static state, and a low-side intermediate drive source signal that approximates common in the first static state and approximates VSS in the opposite static state, the level shifter further comprising a supply impedance Zs of magnitude greater than 1000 ohms at a frequency inverse of an input to output transition time duration for the level shifter front end stage, Zs disposed such that coupling of any such intermediate drive source signal to a selected supply that is either VDD or VSS is coupled to such selected supply via series connection with Zs.

9. The level shifter of claim 8, further comprising significant non-parasitic capacitance disposed between the high-side intermediate drive source signal and the low-side intermediate drive source signal of each pair.

10. The level shifter of claim 1, further comprising a transmission gate and a clamping circuit both controlled by a source drive output to interrupt and clamp a signal maintaining a different source drive output “

at common”

.

11. A method of developing, in a level shifter circuit, at least one final output signal that substantially approaches an upper supply rail voltage VDD in a first static state and substantially approaches a lower supply rail voltage VSS in an opposite second static state, the state controlled by an input control signal to the level shifter that falls suitably within an input control signal range that is substantially smaller than the range from VDD to VSS, the method comprising the steps of:

a) producing the final output signal in a corresponding final output drive block;

b) coupling a high side source supply signal output from a high side source supply driver to the final output drive block wherein the high side source supply signal is “

at a rail” and

approximates VDD in one static state, and is “

at common”

approximating common voltage in the opposite static state;

c) coupling a low side source supply signal output to the final output drive block, wherein the low side source supply signal output is “

at common” and

approximates common voltage in the one static state, and is “

at a rail”

approximating VSS in the opposite static state; and

d) during each transition between the two opposite states initiated by an input change, delaying initiation of a transition by a source supply signal output that is “

at common”

until after a source supply signal output that is “

at a rail”

has significantly transitioned toward common.

12. The method of claim 11, further comprising providing, from first and second final output driver blocks both controlled by the input control signal, first and second differential final outputs that are inverted with respect to each other, including coupling to each of the two differential final output driver blocks a pair of source supply outputs including both a high side source supply output and a low side source supply output, wherein

i) in one static state the high side source supply output coupled to one of the two final output driver blocks is “

at a rail”

approximating VDD while the high side source supply output coupled to the other of the two final output driver blocks is “

at common”

, and in the opposite static state these two high side source supply outputs are respectively “

at common”

approximating common voltage, and “

at a rail”

approximating VDD, and

ii) in the one static state the low side source supply output coupled to the one of the two final output driver blocks is “

at common”

approximating common voltage while the low side source supply output coupled to the other of the two final output driver blocks is “

at a rail”

approximating VSS, and in the opposite static state these two low side source supply outputs are respectively “

at a rail”

approximating VSS and “

at common”

approximating common voltage.

13. The method of claim 12, further comprising preventing, for each source supply output that is “

at common”

, initiation of a transition toward “

at a rail”

until after a source supply output has completed a significant portion of a transition from “

at a rail”

toward “

at common”

.

14. The method of claim 12, further comprising preventing initiation of a transition of either source supply output from “

at common”

toward “

at a rail”

until after a source supply output coupled to a different final output driver block has transitioned substantially from “

at a rail”

toward “

at common”

.

15. The method of claim 12, further comprising preventing initiation of a transition of either source supply output away from “

at common”

toward “

at a rail”

until after a source supply output coupled to a same final output driver block has transitioned substantially from “

at a rail”

toward “

at common”

.

16. The method of claim 11, wherein the level shifter has two stages including a front end level shifter stage that produces two pairs of intermediate source supply signals, one of the two pairs consisting of a high level intermediate source supply signal that is “

at common”

approximating common in a static state A and “

at a rail”

approximating VDD in an opposite static state B and a low level intermediate source supply signal that is “

at a rail”

approximating VSS in the state A and “

at common”

approximating common in the state B, the other of the two pairs consisting of a high level intermediate source supply signal that is “

at a rail”

approximating VDD in the state A and “

at common”

approximating common in the state B, and a low level intermediate source supply signal that is “

at common”

approximating common in the state A and “

at a rail”

approximating VSS in the state B.

17. The method of claim 16, further comprising disposing a significant non-parasitic capacitor between the high and low level intermediate supply signals of each pair of such supply signals.

18. The method of claim 16, further comprising coupling a selected supply, either VDD or VSS, to any high or low level intermediate supply signal of a front end level shifter stage only via a series impedance Zs common to all such couplings to the selected supply.

19. The method of claim 18, further comprising disposing a significant non-parasitic capacitor between the high and low level intermediate supply signals of each pair of such supply signals.

20. The method of claim 11, further comprising delaying initiation of a transition by a source supply signal output that is “

at common”

by interrupting a signal that establishes the source supply signal output “

at common” and

clamping such signal to a level maintaining the source supply signal output “

at common”

until the signal is unclamped by a source supply signal output significantly transitioning from “

at a rail”

toward common.