Integrated Circuit Structure, Design Structure, and Method Having Improved Isolation and Harmonics

• US 20100035403A1
• Filed: 08/07/2008
• Published: 02/11/2010
• Est. Priority Date: 08/07/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Elliott, James R., Joseph, Alvin J., Brown, Brennan J.
• Granted Patent: US 7,927,963 B2
• Time in Patent Office: Days
• US Class Current: 438/422
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a wafer comprising;

a semiconductor substrate comprising a single crystalline semiconductor material;

an insulating layer on said semiconductor substrate;

a semiconductor layer on said insulating layer; and

a shallow trench isolation region within said semiconductor layer on said insulating layer;

etching a trench extending through said shallow trench isolation region and said insulating layer and stopping at a top surface of said semiconductor substrate;

implanting inert ions into said semiconductor substrate so as to form an at least partially amorphized region of said semiconductor substrate adjacent to a bottom surface of said trench; and

filling said trench with a dielectric material so as to form a deep trench isolation region.

2. The method according to claim 1, said implanting comprising implanting at least one of argon ions, krypton ions, xenon ions, nitrogen ions, neon ions, carbon ions, and oxygen ions.

3. The method according to claim 1, further comprising, before said etching of said trench, forming at least one integrated circuit device in said semiconductor layer and patterning said trench to so that said trench is positioned outside lateral boundaries of said at least one integrated circuit device.

4. The method according to claim 1, further comprising, after said filling of said trench to form said deep trench isolation region, forming at least one wiring layer above said semiconductor layer and forming at least one integrated circuit device in said at least one wiring layer such that said deep trench isolation region is positioned outside lateral boundaries of said at least one integrated circuit device.

5. The method according to claim 1, said filling of said trench comprising performing a chemical vapor deposition process to fill said trench with borophosphosilicate glass (BPSG).

6. The method according to claim 5, said filling of said trench comprising, before said performing of said chemical vapor deposition process, lining said trench with one of an oxide and a nitride.

7. A method of forming a semiconductor structure, said method comprising:

providing a wafer comprising;

a semiconductor substrate comprising a single crystalline semiconductor material;

an insulating layer on said semiconductor substrate;

a semiconductor layer on said insulating layer; and

a shallow trench isolation region within said semiconductor layer on said insulating layer;

etching a trench extending through said shallow trench isolation region and said insulating layer and stopping a predetermined depth within said semiconductor substrate;

implanting inert ions into said semiconductor substrate so as to form an at least partially amorphized region of said semiconductor substrate adjacent a bottom surface of said trench; and

filling said trench with a dielectric material so as to form a deep trench isolation region.

8. The method according to claim 7, said implanting comprising implanting at least one of argon ions, krypton ions, nitrogen ions, xenon ions, neon ions, carbon ions, and oxygen ions.

9. The method according to claim 7, further comprising, before said etching of said trench, forming at least one integrated circuit device in said semiconductor layer and patterning said trench such that said trench is positioned outside lateral boundaries of said at least one integrated circuit device.

10. The method according to claim 7, further comprising, after said filling of said trench to form said deep trench isolation region, forming at least one wiring layer above said semiconductor layer and forming at least one integrated circuit device in said at least one wiring layer such that said deep trench isolation region is positioned outside lateral boundaries of said at least one integrated circuit device.

11. The method according to claim 7, said filling of said trench comprising performing a chemical vapor deposition process to fill said trench with borophosphosilicate glass (BPSG).

12. The method according to claim 11, said filling of said trench comprising, before said performing of said chemical vapor deposition process, lining said trench with one of an oxide and a nitride.

13. A method of forming a semiconductor structure, said method comprising:

providing a wafer comprising;

a semiconductor substrate comprising a single crystalline semiconductor material;

an insulating layer on said semiconductor substrate; and

a semiconductor layer on said insulating layer;

forming a shallow trench isolation region within said semiconductor layer and a first deep trench isolation region extending through said semiconductor layer and said insulator layer to said semiconductor substrate such that said shallow trench isolation region and said first deep trench isolation region are separated by semiconductor material and such that said first deep trench isolation region comprises a different material than said insulating layer and said shallow trench isolation region, said forming defining an integrated circuit device area of said wafer;

etching a trench extending through said shallow trench isolation region and said insulating layer and stopping one of at a top surface of said semiconductor substrate and a predetermined depth within said semiconductor substrate;

implanting inert ions into said semiconductor substrate so as to form an at least partially amorphized region of said semiconductor substrate adjacent to a bottom surface of said trench;

performing an isotropic etch process to selectively remove a portion of said insulating layer and said shallow trench isolation region within said integrated circuit device area of said wafer so as to create an air gap between said semiconductor layer and said semiconductor substrate and an opening within said semiconductor layer extending to said air gap; and

depositing a dielectric material through said opening and into said air gap so as to form a second deep trench isolation region.

14. The method according to claim 13, said shallow trench isolation region being patterned such that after said performing of said isotropic etch at least one section of said semiconductor layer within said integrated circuit device area of said wafer remains intact extending to said first deep trench isolation region for mechanical stability.

15. The method according to claim 13, said implanting comprising implanting at least one of argon ions, krypton ions, nitrogen ions, xenon ions, neon ions, carbon ions, and oxygen ions.

16. The method according to claim 13, further comprising, before said etching of said trench, forming at least one integrated circuit device in said semiconductor layer within said integrated circuit device area of said wafer.

17. The method according to claim 13, further comprising, after said filling of said trench to form said second deep trench isolation region, forming at least one wiring layer above said semiconductor layer within said integrated circuit device area of said wafer and forming at least one integrated circuit device in said at least one wiring layer such that said second deep trench isolation region is positioned outside lateral boundaries of said at least one integrated circuit device.

18. The method according to claim 13, said filling of said trench comprising performing a chemical vapor deposition process to fill said trench with borophosphosilicate glass (BPSG).

19. The method according to claim 18, said filling of said trench comprising, before said performing of said chemical vapor deposition process, lining said trench with one of an oxide and a nitride.